[31:2]
Reserved
SPI Flash Interface Control Register (
When the
en
bit of the
fctrl
register is set, the controller enters direct memory-mapped SPI
flash mode. Accesses to the direct-mapped memory region causes the controller to automati-
cally sequence SPI flash reads in hardware. The reset value is
0x1
. See Table 85.
SPI Flash Interface Control Register (
fctrl
)
Register Offset
0x60
Bits
Field Name
Attr.
Rst.
Description
0
en
RW
0x1
SPI Flash Mode Select
[31:1]
Reserved
SPI Flash Instruction Format Register (
The
ffmt
register defines the format of the SPI flash read instruction issued by the controller
when the direct-mapped memory region is accessed while in SPI flash mode.
An instruction consists of a command byte followed by a variable number of address bytes,
dummy cycles (padding), and data bytes. Table 86 describes the function and reset value of
each field.
SPI Flash Instruction Format Register (
ffmt
)
Register Offset
0x64
Bits
Field Name
Attr.
Rst.
Description
0
cmd_en
RW
0x1
Enable sending of command
[3:1]
addr_len
RW
0x3
Number of address bytes (0 to 4)
[7:4]
pad_cnt
RW
0x0
Number of dummy cycles
[9:8]
cmd_proto
RW
0x0
Protocol for transmitting command
[11:10]
addr_proto
RW
0x0
Protocol for transmitting address and padding
Table 84:
SPI Watermark Interrupt Pending Register
Table 85:
SPI Flash Interface Control Register
Table 86:
SPI Flash Instruction Format Register
Chapter 18 Serial Peripheral Interface (SPI)
FE310-G003 Manual
© SiFive, Inc.
Page 97
Содержание FE310-G003
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