The programmed-I/O interface exposes the OTP device’s and power-supply’s control signals
directly to software. Software is responsible for respecting these signals' setup and hold times.
The OTP device requires that data be programmed one bit at a time and that the result be re-
read and retried according to a specific protocol.
See the OTP device and power supply data sheets for timing constraints, control signal descrip-
tions, and the programming algorithm.
Read sequencer control register (
The read sequence consists of an address-setup phase, a read-pulse phase, and a read-access
phase. The duration of these phases, in terms of controller clock cycles, is set by a programma-
ble clock divider. The divider is controlled by the
otp_rsctrl
register, the layout of which is
shown in Table 34.
The number of clock cycles in each phase is given by
, and the width of each phase may
be optionally scaled by 3. That is, the number of controller clock cycles in the address-setup
phase is given by the expression
; the number of clock cycles in the read-
pulse phase is given by
; and the read-access phase is
cycles long.
Software should acquire the
otp_lock
prior to modifying
otp_rsctrl
.
otp_rsctrl: OTP read sequencer control (
otp_rsctrl
)
Register Offset
0x34
Bits
Field Name
Attr.
Rst.
Description
[2:0]
scale
RW
0x1
OTP timescale
3
tas
RW
0x0
Address setup time
4
trp
RW
0x0
Read pulse time
5
tacc
RW
0x0
Read access time
[31:6]
Reserved
Table 34:
otp_rsctrl: OTP read sequencer control
Chapter 11 One-Time Programmable Memory (OTP)
FE310-G003 Manual
© SiFive, Inc.
Page 55
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