Table 63:
SPI Instances
Instance
Flash Controller
Address
cs_width
div_width
SPI 1
N
0x10024000
4
12
SPI 2
N
0x10034000
1
12
The memory map for the SPI control registers is shown in Table 64. The SPI memory map has
been designed to require only naturally-aligned 32-bit memory accesses.
Offset
Name
Description
0x00
sckdiv
Serial clock divisor
0x04
sckmode
Serial clock mode
0x08
Reserved
0x0C
Reserved
0x10
csid
Chip select ID
0x14
csdef
Chip select default
0x18
csmode
Chip select mode
0x1C
Reserved
0x20
Reserved
0x24
Reserved
0x28
delay0
Delay control 0
0x2C
delay1
Delay control 1
0x30
Reserved
0x34
Reserved
0x38
Reserved
0x3C
Reserved
0x40
fmt
Frame format
0x44
Reserved
Table 64:
Register offsets within the SPI memory map. Registers marked * are present only on
controllers with the direct-map flash interface.
Chapter 18 Serial Peripheral Interface (SPI)
FE310-G003 Manual
© SiFive, Inc.
Page 88
Содержание FE310-G003
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