SiFive E31 Core Complex Manual
Proprietary Notice
Copyright © 2017–2018, SiFive Inc. All rights reserved.
Information in this document is provided “as is,” with all faults.
SiFive expressly disclaims all warranties, representations, and conditions of any kind, whether
express or implied, including, but not limited to, the implied warranties or conditions of mer-
chantability, fitness for a particular purpose and non-infringement.
SiFive does not assume any liability rising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation indirect, incidental, spe-
cial, exemplary, or consequential damages.
SiFive reserves the right to make changes without further notice to any products herein.
Release Information
Version
Date
Changes
v2p0
June 01, 2018
• Updated E31 Core Complex definition; 4 hw
breakpoints and 127 Global interrupts.
• Moved Interface and Debug Interface chapters
to User Guide.
v1p2
October 11, 2017
• Core Complex branding
• Added references
• Updated interrupt chapter
v1p1
August 25, 2017
• Updated text descriptions
• Updated register and memory map tables for
consistency
v1p0
May 04, 2017
• Initial release
• Describes the functionality of the SiFive E31
Core Complex