Platform-Level Interrupt Controller
(PLIC)
This chapter describes the operation of the platform-level interrupt controller (PLIC) on the E31
Core Complex. The PLIC complies with
The RISC‑V Instruction Set Manual, Volume II: Privi-
leged Architecture, Version 1.10
and can support a maximum of 127 external interrupt sources
with 7 priority levels.
The E31 Core Complex PLIC resides in the
clock
timing domain, allowing for relaxed timing
requirements. The latency of global interrupts, as perceived by a hart, increases with the ratio of
the
core_clock_0
frequency and the
clock
frequency.
The memory map for the E31 Core Complex PLIC control registers is shown in Table 13. The
PLIC memory map has been designed to only require naturally aligned 32-bit memory
accesses.
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