By default, all interrupts trap to a single address defined in the
mtvec
register. It is up to the
interrupt handler to read
mcause
and react accordingly. RISC‑V and the E31 Core Complex also
support the ability to optionally enable interrupt vectors. When vectoring is enabled, each inter-
rupt defined in
mie
will trap to its own specific interrupt handler. This allows all local interrupts to
trap to exclusive handlers. Even with vectoring enabled, all global interrupts will trap to the same
global interrupt vector.
Vectored interrupts are enabled when the MODE field of the
mtvec
register is set to 1.
Machine Trap Vector Register
CSR
mtvec
Bits
Field Name
Attr.
Description
[1:0]
MODE
WARL
MODE
determines whether or not interrupt
vectoring is enabled. The encoding for the
MODE
field is described in Table 11.
[31:2]
BASE[31:2]
WARL
Interrupt Vector Base Address. Must be
aligned on a 128-byte boundary when
MODE=1. Note, BASE[1:0] is not present in
this register and is implicitly 0.
Table 10:
mtvec
Register
MODE Field Encoding
mtvec.MODE
Value
Name
Description
0
Direct
All exceptions set
pc
to
BASE
1
Vectored
Asynchronous interrupts set
pc
to
BASE
+ 4 ×
cause.
≥ 2
Reserved
Table 11:
Encoding of
mtvec.MODE
If vectored interrupts are disabled (
mtvec.MODE
=0), all interrupts trap to the
mtvec.BASE
address. If vectored interrupts are enabled (
mtvec.MODE
=1), interrupts set the
pc
to
mtvec.BASE
+ 4 × exception code. For example, if a machine timer interrupt is taken, the
pc
is
set to
mtvec.BASE
+ 0x1C. Typically, the trap vector table is populated with jump instructions to
transfer control to interrupt-specific trap handlers.
In vectored interrupt mode, BASE must be 128-byte aligned.
All machine external interrupts (global interrupts) are mapped to exception code of 11. Thus,
when interrupt vectoring is enabled, the
pc
is set to address
mtvec.BASE
+ 0x2C for any global
interrupt.
See Table 10 for a description of the
mtvec
register. See Table 11 for a description of the
mtvec.MODE
field. See Table 9 for the E31 Core Complex interrupt exception code values.
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