• MUL, MULH, MULHU, and MULHSU have a 2-cycle result latency.
• DIV, DIVU, REM, and REMU have between a 2-cycle and 33-cycle result latency, depending
on the operand values.
The pipeline only interlocks on read-after-write and write-after-write hazards, so instructions
may be scheduled to avoid stalls.
The E31 implements the standard Multiply (M) extension to the RISC‑V architecture for integer
multiplication and division. The E31 has a 32-bit per cycle hardware multiply and a 1-bit per
cycle hardware divide. The multiplier is fully pipelined and can begin a new operation on each
cycle, with a maximum throughput of one operation per cycle.
Branch and jump instructions transfer control from the memory access pipeline stage. Correctly-
predicted branches and jumps incur no penalty, whereas mispredicted branches and jumps
incur a three-cycle penalty.
Most CSR writes result in a pipeline flush with a five-cycle penalty.
The E31 data memory system consists of a DTIM interface, which supports up to 64 KiB. The
access latency from a core to its own DTIM is two clock cycles for full words and three clock
cycles for smaller quantities. Misaligned accesses are not supported in hardware and result in a
trap to allow software emulation.
Stores are pipelined and commit on cycles where the data memory system is otherwise idle.
Loads to addresses currently in the store pipeline result in a five-cycle penalty.
The E31 core supports the RISC‑V standard Atomic (A) extension on the DTIM and the Periph-
eral Port. Atomic memory operations to regions that do not support them generate an access
exception precisely at the core.
The load-reserved and store-conditional instructions are only supported on cached regions,
hence generate an access exception on DTIM and other uncached memory regions.
See
The RISC‑V Instruction Set Manual, Volume I: User-Level ISA, Version 2.1
for more infor-
mation on the instructions added by this extension.
The E31 supports up to 16 local interrupt sources that are routed directly to the core. See Chap-
ter 5 for a detailed description of Local Interrupts.
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