When implementing less than the maximum DTIM RAM, a PMP region encompassing the unim-
plemented address space must be locked with no R/W/X permissions. Doing so forces all
access to the unimplemented address space to generate an exception.
For example, if implementing 32 KiB of DTIM RAM, then setting
pmp0cfg
=0x98 and
pmpaddr0
=0x2000_0FFF disables access to the unimplemented 32 KiB region above.
The E31 Core Complex supports a basic hardware performance monitoring facility compliant
with
The RISC‑V Instruction Set Manual, Volume II: Privileged Architecture, Version 1.10
. The
mcycle
CSR holds a count of the number of clock cycles the hart has executed since some
arbitrary time in the past. The
minstret
CSR holds a count of the number of instructions the
hart has retired since some arbitrary time in the past. Both are 64-bit counters. The
mcycle
and
minstret
CSRs hold the 32 least-significant bits of the corresponding counter, and the
mcycleh
and
minstreth
CSRs hold the most-significant 32 bits.
The hardware performance monitor includes two additional event counters,
mhpmcounter3
and
mhpmcounter4
. The event selector CSRs
mhpmevent3
and
mhpmevent4
are registers that con-
trol which event causes the corresponding counter to increment. The
mhpmcounters
are 40-bit
counters. The
mhpmcounter_i
CSR holds the 32 least-significant bits of the corresponding
counter, and the
mhpmcounter_ih
CSR holds the 8 most-significant bits.
The event selectors are partitioned into two fields, as shown in Table 3: the lower 8 bits select
an event class, and the upper bits form a mask of events in that class. The counter increments if
the event corresponding to any set mask bit occurs. For example, if
mhpmevent3
is set to
0x4200
, then
mhpmcounter3
will increment when either a load instruction or a conditional
branch instruction retires. Note that an event selector of 0 means "count nothing."
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