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Figure 1:

E31 Core Complex Block Diagram

The E31 Core Complex memory map is detailed in Chapter 4, and the interfaces are described
in full in the E31 Core Complex User Guide.

E31 RISC‑V Core

The E31 Core Complex includes a 32-bit E31 RISC‑V core, which has a high-performance sin-
gle-issue in-order execution pipeline, with a peak sustainable execution rate of one instruction
per clock cycle. The E31 core supports Machine and User privilege modes as well as standard
Multiply, Atomic, and Compressed RISC‑V extensions (RV32IMAC).

The core is described in more detail in Chapter 3.

Debug Support

The E31 Core Complex provides external debugger support over an industry-standard JTAG
port, including 4 hardware-programmable breakpoints per hart.

Copyright © 2017–2018, SiFive Inc. All rights reserved.

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Содержание E31

Страница 1: ...SiFive E31 Core Complex Manual v2p0 SiFive Inc ...

Страница 2: ...rcuit and specifically disclaims any and all liability including without limitation indirect incidental spe cial exemplary or consequential damages SiFive reserves the right to make changes without further notice to any products herein Release Information Version Date Changes v2p0 June 01 2018 Updated E31 Core Complex definition 4 hw breakpoints and 127 Global interrupts Moved Interface and Debug ...

Страница 3: ...econfigurability 9 3 2 Instruction Fetch Unit 9 3 3 Execution Pipeline 9 3 4 Data Memory System 10 3 5 Atomic Memory Operations 10 3 6 Local Interrupts 10 3 7 Supported Modes 11 3 8 Physical Memory Protection PMP 11 3 8 1 Functional Description 11 3 8 2 Region Locking 11 3 9 Hardware Performance Monitor 12 4 Memory Map 14 5 Interrupts 15 5 1 Interrupt Concepts 15 5 2 Interrupt Entry and Exit 16 5 ...

Страница 4: ... Controller PLIC 24 7 1 Memory Map 24 7 2 Interrupt Sources 25 7 3 Interrupt Priorities 26 7 4 Interrupt Pending Bits 26 7 5 Interrupt Enables 27 7 6 Priority Thresholds 28 7 7 Interrupt Claim Process 28 7 8 Interrupt Completion 28 8 Debug 30 8 1 Debug CSRs 30 8 1 1 Trace and Debug Register Select tselect 30 8 1 2 Trace and Debug Data Registers tdata1 3 31 8 1 3 Debug Control and Status Register d...

Страница 5: ...ng Breakpoints Between Debug and Machine Mode 35 8 3 Debug Memory Map 35 8 3 1 Debug RAM and Program Buffer 0x300 0x3FF 35 8 3 2 Debug ROM 0x800 0xFFF 35 8 3 3 Debug Flags 0x100 0x110 0x400 0x7FF 36 8 3 4 Safe Zero Address 36 9 References 37 3 ...

Страница 6: ...can be connected to off core complex devices PLIC Interrupts 127 Interrupt signals which can be connected to off core complex devices PLIC Priority Levels The PLIC supports 7 priority levels Hardware Breakpoints 4 hardware breakpoints Physical Memory Protection Unit PMP with 8 x regions and a minimum granularity of 4 bytes Table 1 E31 Core Complex Feature Set 1 1 E31 Core Complex Overview An overv...

Страница 7: ...der execution pipeline with a peak sustainable execution rate of one instruction per clock cycle The E31 core supports Machine and User privilege modes as well as standard Multiply Atomic and Compressed RISC V extensions RV32IMAC The core is described in more detail in Chapter 3 1 3 Debug Support The E31 Core Complex provides external debugger support over an industry standard JTAG port including ...

Страница 8: ...d software interrupts via the Core Local Interruptor CLINT Interrupts are described in Chapter 5 The CLINT is described in Chapter 6 The PLIC is described in in Chapter 7 1 5 Memory System The E31 Core Complex memory system has Tightly Integrated Instruction and Data Memory sub systems optimized for high performance The instruction subsystem consists of a 16 KiB 2 way instruction cache with the ab...

Страница 9: ...andard originally developed at UC Berke ley RO Used to describe a Read Only register field RW Used to describe a Read Write register field WO Used to describe a Write Only registers field WARL Write Any Read Legal field A register field that can be written with any value but returns only supported values when read WIRI Writes Ignored Reads Ignore field A read only register field reserved for futur...

Страница 10: ...system consists of a dedicated 16 KiB 2 way set associative instruction cache The access latency of all blocks in the instruction memory system is one clock cycle The instruction cache is not kept coherent with the rest of the platform memory system Writes to instruction memory must be synchronized with the instruction fetch stream by executing a FENCE I instruction The instruction cache has a lin...

Страница 11: ...e preserved between deallocation and allocation 3 2 Instruction Fetch Unit The E31 instruction fetch unit contains branch prediction hardware to improve performance of the processor core The branch predictor comprises a 28 entry branch target buffer BTB which predicts the target of taken branches a 512 entry branch history table BHT which predicts the direction of conditional branches and a 6 entr...

Страница 12: ... supports up to 64 KiB The access latency from a core to its own DTIM is two clock cycles for full words and three clock cycles for smaller quantities Misaligned accesses are not supported in hardware and result in a trap to allow software emulation Stores are pipelined and commit on cycles where the data memory system is otherwise idle Loads to addresses currently in the store pipeline result in ...

Страница 13: ...ludes a PMP unit which can be used to restrict access to memory and isolate processes from each other The E31 PMP unit has 8 regions and a minimum granularity of 4 bytes Overlapping regions are permitted The E31 PMP unit implements the architecturally defined pmpcfgX CSRs pmpcfg0 and pmpcfg1 supporting 8 regions pmpcfg2 and pmpcfg3 are implemented but hardwired to zero The PMP registers may only b...

Страница 14: ... and minstret CSRs hold the 32 least significant bits of the corresponding counter and the mcycleh and minstreth CSRs hold the most significant 32 bits The hardware performance monitor includes two additional event counters mhpmcounter3 and mhpmcounter4 The event selector CSRs mhpmevent3 and mhpmevent4 are registers that con trol which event causes the corresponding counter to increment The mhpmco...

Страница 15: ...tion instruction retired 18 Integer division instruction retired Microarchitectural Events mhpeventX 7 0 1 Bits Meaning 8 Load use interlock 9 Long latency interlock 10 CSR read interlock 11 Instruction cache ITIM busy 12 Data cache DTIM busy 13 Branch direction misprediction 14 Branch jump target misprediction 15 Pipeline flush from CSR write 16 Pipeline flush from other event 17 Integer multipli...

Страница 16: ...0800_2000 0x0BFF_FFFF Reserved 0x0C00_0000 0x0FFF_FFFF RW A PLIC 0x1000_0000 0x1FFF_FFFF Reserved On Core Complex Devices 0x2000_0000 0x3FFF_FFFF RWX A Peripheral Port 512 MiB 0x4000_0000 0x5FFF_FFFF RWX System Port 512 MiB 0x6000_0000 0x7FFF_FFFF Reserved Off Core Complex Address Space for Exter nal I O 0x8000_0000 0x8000_FFFF RWX A Data Tightly Integrated Memory DTIM 64 KiB 0x8001_0000 0xFFFF_FF...

Страница 17: ...t and no additional memory accesses are required to determine the cause of the interrupt Software and timer interrupts are local interrupts generated by the Core Local Interruptor CLINT Global interrupts by contrast are routed through a Platform Level Interrupt Controller PLIC which can direct interrupts to any hart in the system via the external interrupt Decoupling global interrupts from the har...

Страница 18: ... to the interrupt is encoded in mstatus MPP At this point control is handed over to software in the interrupt handler with interrupts disabled Interrupts can be re enabled by explicitly setting mstatus MIE or by executing an MRET instruc tion to exit the handler When an MRET instruction is executed the following occurs The privilege mode is set to the value encoded in mstatus MPP The value of msta...

Страница 19: ...ields unrelated to interrupts For the full description of mstatus please consult the The RISC V Instruction Set Manual Volume II Privileged Architecture Version 1 10 Machine Status Register CSR mstatus Bits Field Name Attr Description 2 0 Reserved WPRI 3 MIE RW Machine Interrupt Enable 6 4 Reserved WPRI 7 MPIE RW Machine Previous Interrupt Enable 10 8 Reserved WPRI 12 11 MPP RW Machine Previous Pr...

Страница 20: ...ne Interrupt Pending Register CSR mip Bits Field Name Attr Description 2 0 Reserved WIRI 3 MSIP RO Machine Software Interrupt Pending 6 4 Reserved WIRI 7 MTIP RO Machine Timer Interrupt Pending 10 8 Reserved WIRI 11 MEIP RO Machine External Interrupt Pending 15 12 Reserved WIRI 16 LIP0 RO Local Interrupt 0 Pending 17 LIP1 RO Local Interrupt 1 Pending 18 LIP2 RO Local Interrupt 2 Pending 31 LIP15 R...

Страница 21: ...upt 0 otherwise Table 8 mcause Register Interrupt Exception Codes Interrupt Exception Code Description 1 0 2 Reserved 1 3 Machine software interrupt 1 4 6 Reserved 1 7 Machine timer interrupt 1 8 10 Reserved 1 11 Machine external interrupt 1 12 15 Reserved 1 16 Local Interrupt 0 1 17 Local Interrupt 1 1 18 30 1 31 Local Interrupt 15 1 32 Reserved 0 0 Instruction address misaligned 0 1 Instruction ...

Страница 22: ...is not present in this register and is implicitly 0 Table 10 mtvec Register MODE Field Encoding mtvec MODE Value Name Description 0 Direct All exceptions set pc to BASE 1 Vectored Asynchronous interrupts set pc to BASE 4 cause 2 Reserved Table 11 Encoding of mtvec MODE If vectored interrupts are disabled mtvec MODE 0 all interrupts trap to the mtvec BASE address If vectored interrupts are enabled ...

Страница 23: ...Individual priorities of global interrupts are determined by the PLIC as discussed in Chapter 7 E31 Core Complex interrupts are prioritized as follows in decreasing order of priority Local Interrupt 15 Local Interrupt 0 Machine external interrupts Machine software interrupts Machine timer interrupts 5 5 Interrupt Latency Interrupt latency for the E31 Core Complex is 4 cycles as counted by the numb...

Страница 24: ...timecmp for hart 0 MTIMECMP Registers 0x204008 0x20bff7 Reserved 0x20bff8 8B RW mtime Timer Register 0x20c000 Reserved Table 12 CLINT Register Map 6 2 MSIP Registers Machine mode software interrupts are generated by writing to the memory mapped control reg ister msip Each msip register is a 32 bit wide WARL register where the upper 31 bits are tied to 0 The least significant bit is reflected in th...

Страница 25: ... Core Complex User Guide A timer interrupt is pending whenever mtime is greater than or equal to the value in the mtimecmp register The timer inter rupt is reflected in the mtip bit of the mip register described in Chapter 5 On reset mtime is cleared to zero The mtimecmp registers are not reset Copyright 2017 2018 SiFive Inc All rights reserved 23 ...

Страница 26: ... of 127 external interrupt sources with 7 priority levels The E31 Core Complex PLIC resides in the clock timing domain allowing for relaxed timing requirements The latency of global interrupts as perceived by a hart increases with the ratio of the core_clock_0 frequency and the clock frequency 7 1 Memory Map The memory map for the E31 Core Complex PLIC control registers is shown in Table 13 The PL...

Страница 27: ...n 7 6 for more information 0x0C20_0004 4B RW Hart 0 M Mode claim com plete See Section 7 7 for more information 0x0C20_0008 Reserved 0x1000_0000 End of PLIC Memory Map Table 13 SiFive PLIC Register Map Only naturally aligned 32 bit memory accesses are required 7 2 Interrupt Sources The E31 Core Complex has 127 interrupt sources These are exposed at the top level via the global_interrupts signals A...

Страница 28: ...isters 7 4 Interrupt Pending Bits The current status of the interrupt source pending bits in the PLIC core can be read from the pending array organized as 4 words of 32 bits The pending bit for interrupt ID is stored in bit of word As such the E31 Core Complex has 4 interrupt pending regis ters Bit 0 of word 0 which represents the non existent interrupt source 0 is hardwired to zero A pending bit ...

Страница 29: ...he enables array in SiFive RV32 systems PLIC Interrupt Enable Register 1 enable1 for Hart 0 M Mode Base Address 0x0C00_2000 Bits Field Name Attr Rst Description 0 Interrupt 0 Enable RO 0 Non existent global interrupt 0 is hard wired to zero 1 Interrupt 1 Enable RW X Enable bit for global interrupt 1 2 Interrupt 2 Enable RW X Enable bit for global interrupt 2 31 Interrupt 31 Enable RW X Enable bit ...

Страница 30: ... claim complete regis ter Table 20 which returns the ID of the highest priority pending interrupt or zero if there is no pending interrupt A successful claim also atomically clears the corresponding pending bit on the interrupt source A E31 Core Complex hart can perform a claim at any time even if the MEIP bit in its mip Table 7 register is not set The claim operation is not affected by the settin...

Страница 31: ... A read of zero indicates that no inter rupts are pending A non zero read contains the id of the highest pending interrupt A write to this register signals completion of the interrupt id written Table 20 PLIC Interrupt Claim Complete Register for Hart 0 M Mode Copyright 2017 2018 SiFive Inc All rights reserved 29 ...

Страница 32: ...d TDR D M tdata3 Third field of selected TDR D M dcsr Debug control and status register D dpc Debug PC D dscratch Debug scratch register D Table 21 Debug Control and Status Registers The dcsr dpc and dscratch registers are only accessible in debug mode while the tselect and tdata1 3 registers are accessible from either debug mode or machine mode 8 1 1 Trace and Debug Register Select tselect To sup...

Страница 33: ...ta Register 1 CSR tdata1 Bits Field Name Attr Description 27 0 TDR Specific Data 31 28 type RO Type of the trace debug register selected by tselect Table 23 tdata1 CSR Trace and Debug Data Registers 2 and 3 CSR tdata2 3 Bits Field Name Attr Description 31 0 TDR Specific Data Table 24 tdata2 3 CSRs The high nibble of tdata1 contains a 4 bit type code that is used to identify the type of TDR selecte...

Страница 34: ...g ROM The debugger may use it as described in The RISC V Debug Specifi cation 0 13 8 2 Breakpoints The E31 Core Complex supports four hardware breakpoint registers per hart which can be flex ibly shared between debug mode and machine mode When a breakpoint register is selected with tselect the other CSRs access the following infor mation for the selected breakpoint CSR Name Breakpoint Alias Descri...

Страница 35: ...ies the available actions when the address match is successful The value 0 generates a breakpoint exception The value 1 enters debug mode Other actions are not implemented The R W X bits are individual WARL fields and if set indicate an address match should only be successful for loads stores instruction fetches respectively and all combinations of imple mented bits must be supported The M S U bit...

Страница 36: ...set to 1 bit 30 set to 0 and bit 31 holding the only address bit considered in the address comparison To provide breakpoints on an exact range two neighboring breakpoints can be combined with the chain bit The first breakpoint can be set to match on an address using action of 2 greater than or equal The second breakpoint can be set to match on address using action of 3 less than Setting the chain ...

Страница 37: ...mined by executing aiupc instructions and storing the result into the program buffer The E31 Core Complex has one 32 bit words of debug data RAM Its location can be deter mined by reading the DMHARTINFO register as described in the RISC V Debug Specification This RAM space is used to pass data for the Access Register abstract command described in the RISC V Debug Specification The E31 Core Complex...

Страница 38: ...y program buffer code The specific behavior of the flags is not further documented here 8 3 4 Safe Zero Address In the E31 Core Complex the debug module contains the address 0x0 in the memory map Reads to this address always return 0 and writes to this address have no impact This property allows a safe location for unprogrammed parts as the default mtvec location is 0x0 Copyright 2017 2018 SiFive ...

Страница 39: ... sifive com 1 A Waterman and K Asanovic Eds The RISC V Instruction Set Manual Volume I User Level ISA Version 2 2 May 2017 Online Available https riscv org specifications 2 The RISC V Instruction Set Manual Volume II Privileged Architecture Version 1 10 May 2017 Online Available https riscv org specifications 37 ...

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