Siemens SIMATIC S7-200, Системное руководство

Страница: 258 / 866

Program instructions
7.6 Counters
S7-200 SMART
258
System Manual, V2.3, 07/2017, A5E03822230-AF
HSC operation
A high-speed counter can be used as the drive for a drum timer, where a shaft rotating at a
constant speed is fitted with an incremental shaft encoder. The shaft encoder provides a
specified number of counts per revolution and a reset pulse that occurs once per revolution.
The clock(s) and the reset pulse from the shaft encoder provide the inputs to the high-speed
counter.
The high-speed counter is loaded with the first of several presets, and the desired outputs
are activated for the time period where the current count is less than the current preset. The
counter is set up to provide an interrupt when the current count is equal to preset and also
when reset occurs.
As each current-count-value-equals-preset-value interrupt event occurs, a new preset is
loaded and the next state for the outputs is set. When the reset interrupt event occurs, the
first preset and the first output states are set, and the cycle is repeated.
Since the program interrupts occur at a much lower rate than the counting rates of the high-
speed counters, precise control of high-speed operations can be implemented with relatively
minor impact to the overall PLC scan cycle time. The method of interrupt attachment allows
each load of a new preset to be performed in a separate interrupt routine for easy state
control. (Alternatively, all interrupt events can be processed in a single interrupt routine.)
HSC input assignments and capabilities
All high-speed counters function the same way for the same mode of operation, but every
mode is not supported for every HSC number. The HSC input connections (clock, direction,
and reset) must use the CPU's integrated input channels as shown in the High-speed
counter summary (Page 260) table. Input channels located on a signal board or an
expansion module cannot be used for high-speed counters.
Note
You must ensure that high-speed counter inputs are correctly filtered and wired, for counting
high frequency signals.
In an S7-200 SMART CPU, all high-speed counter inputs are connected to internal input
filter circuits. The S7-200 SMART default input filter setting is 6.4 ms, which limits the
maximum counting rate to 78 Hz. You must change the filter settings to count higher
frequencies.
Refer to "Noise reduction for high-speed inputs (Page 261)" for details about system block
filter options, maximum counting frequencies, shielding requirements, and external pull-down
circuits.