Sharp FO-4500, Руководство по обслуживанию

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LZ9FJ37A (IC15) Terminal descriptions
PIN I/O Name Function PIN I/O Name Function
1 O DP Dial pulse control 52 I/O D14 System data input/output
2 O DT4 Output port 53 I/O D13 System data input/output
3 O DT3 Output port 54 I/O D12 System data input/output
4 O DT2 Output port 55 I XCS6 Chip select 6 signal input
5 O DT1 Output port 56 I XCS2 Chip select 2 signal input
6 O BZ Buzzer output 57 I/O D11 System data input/output
7 O BZSL Output port 58 I/O D10 System data input/output
8 I SDT Input port 59 I/O D9 System data input/output
9 I XRHS Input port 60 I/O D8 System data input/output
10 I XCI Input port 61 — GND Ground
11 I XHS1 Input port 62 — VDD Power supply
12 I XHS2 Input port 63 I/O D7 System data input/output
13 I XEXHS1 Input port 64 I/O D6 System data input/output
14 I XEXHS2 Input port 65 I/O D5 System data input/output
15 O CRNT Output port 66 I/O D4 System data input/output
16 O TXB1 B-phase current control output 1 67 I A19 System address input/output
17 O TXB0 B-phase current control output 0 68 I A20 System address input/output
18 O TXA1 A-phase current control output 1 69 I A21 System address input/output
19 O TXA0 A-phase current control output 0 70 I/O D3 System data input/output
20 — VDD Power supply 71 I/O D2 System data input/output
21 — GND Ground 72 I/O D1 System data input/output
22 O TXPB B-phase current direction setting 73 I/O D0 System data input/output
23 O TXPA A-current direction setting 74 I A6 System address input/output
24 O LEDON LED light source control 75 I A5 System address input/output
25 O PLG1ON Plunger 1 control 76 I A4 System address input/output
26 O PLG0ON Plunger 0 control 77 I A3 System address input/output
27 — GND Ground 78 I A2 System address input/output
28 I CLKR
Sending system control basic clock input
79 I A1 System address input/output
29 I XFLBSY Flash memory busy signal input 80 — GND Ground
30 O FLBK1 Bank control 1 81 I TEST Test terminal
31 O FLBK2 Bank control 2 82 O XSCCLK Reading serial clock
32 O FLBK3 Bank control 3 83 O XSRVID Reading serial data
33 O XFLOPT Chip select (flash option) 84 O XSTVD Reading valid data output gate
34 O XFLSTD Chip select (flash standard) 85 I TXIN Data receiving from SH1
35 O XPGMSL Chip select (EPROM) 86 O RXOUT Data sending to SH1
36 O XSRAM1 Chip select (SRAM option) 87 O TXOUT Data sending signal to PC
37 O XSRAM0 Chip select (SRAM standard) 88 I RXIN Data receiving signal from PC
38 O XINTRQ Interrupt request output 89 O XRTS
Sending of send-ready signal to PC
39 O XREVSL Chip select (spare) 90 O XDSR
Sending of data terminal ready to PC
40 I XRESET System reset 91 I XCTS Sending request from PC
41 — GND Ground 92 I XDTR Data set ready sending to PC
42 I CLKF System clock 93 O XRSCI Call-back to PC
43 O XCDCSL Chip select 94 O XRSCD Carrier detection to PC
44 O XGACSL1 Chip select (spare) 95 I XRSOPT PCI/F presence detection
45 O XGACSL0 Chip select 96 O RTCIO RTC input/output control
46 O XGABSL Chip select (gate array B) 97 O RTCCE RTC chip select
47 O XWR System write output 98 O RTCCK RTC data transfer clock
48 I XRD System read signal 99 I/O RTCDT RTC data input/output
49 I XWRH
System write (high-order byte) signal
100 — VDD Power supply
50 I XWRL System write (low-order byte) signal 101 — GND Ground
51 I/O D15 System data input/output 102 O PHIA CCD clock A
FO-4500H
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