Schweitzer Engineering Laboratories SEL-387-0, Инструкция по эксплуатации

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4.22
SEL-387-0, -5, -6 Relay Instruction Manual
Date Code 20050919
Control Logic
Trip and Close Logic
minimum of TDURD cycles, even if TR1 is asserted for as little as one
processing interval, or if the unlatch portion of the logic is asserted before
TDURD expires. The default setting of TDURD is nine cycles.
TRIP1 also seals itself in via the AND gate at the bottom. This AND gate
receives the negated inputs from the unlatching functions. As long as no
unlatch function is asserted, the seal of TRIP1 remains intact. TRIP1 is used to
drive an output contact to initiate tripping of the breaker or breakers. In our
example, OUT101 = TRIP1.
The unlatching of the trip logic is accomplished via three means. The first is
the assertion of the SEL
OGIC
control equation setting ULTR1. In our example,
ULTR1 = !50P13 = NOT 50P13. This current element is set to pick up at
0.5 A. Thus, ULTR1 asserts when the currents in all three phases drop below
0.5 A, indicating successful three-pole opening of the breaker.
The other unlatching mechanism is manual, via pushing of the
{TARGET RESET}
pushbutton on the front panel or sending the TAR R serial port command to
the relay. Either of these asserts the Relay Word bit TRGTR, which is also
used to reset the LED targets on the front panel. In the trip logic, assertion of
ULTR1 or TRGTR places a zero input on the AND gate and thereby breaks
the TRIP1 seal-in loop.
With the deassertion of TRIP1, OUT101 opens, deenergizing the trip circuit.
Presumably, the trip circuit current has already been interrupted by a breaker
52a contact in series with the trip coil. Should a failure to trip occur, followed
by backup tripping of other breakers, the TR1 setting may deassert and the
ULTR1 setting may assert, while the contact continues to carry dc trip circuit
current. This could damage the contact as it tries to interrupt this current. The
emergency nature of the situation might warrant this minor risk, but another
choice might be to program into the ULTR1 setting not only removal of
current but also indication that the breaker has opened.
Note that TRIP1 will always be asserted so long as TR1 is asserted, regardless
of the action of ULTR1 or the
TARGET RESET commands and that TRIP1
will be asserted for an absolute minimum of TDURD cycles no matter how
short the length of time TR1 has been asserted. This is the essence of the trip
logic.
At the bottom of Figure 4.7 is an additional OR gate. The five TRIP m Relay
Word bits are all inputs to this gate, and the output is another Relay Word bit,
TRIPL. TRIPL asserts for any trip output. It may be useful for other
applications of SEL
OGIC
control equations in the SEL-387.
Close Logic
There are four specific sets of close logic within the SEL-387. They are
designed to operate when SEL
OGIC
control equation close variable setting
CL m is asserted ( m = 1, 2, 3, 4), and to unlatch when SEL
OGIC
control
equation setting ULCL m is asserted. The output of the logic is Relay Word bit
CLS m . The logic operates much like the Latch Bit function in SEL
OGIC
Control Equation Sets 1 through 3 with additional characteristics. In the close
logic, the reset or unlatch function has priority over the set or latch function.
Figure 4.8 shows the logic diagram for the CLS1 logic. The remaining logic
for CLS2 through CLS4 is identical, using variables CL2 through CL4 and
ULCL2 through ULCL4, respectively.