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Status Reporting System R&S®SML / R&S®SMV03
1090.3123.12 E-6 5.16
Status Reporting System
The status reporting system (see Fig. 5-4) stores all information on the current operating state of the
instrument, for example on any errors that have occurred. This information is stored in status registers
and in an error queue. The status registers and the error queue can be queried via the IEC/IEEE bus.
The information is of a hierarchical structure. The highest level is formed by the status byte (STB)
register defined in IEEE 488.2 and the associated service request enable (SRE) mask register. The STB
register receives information from the standard event status register (ESR) which is also defined in IEEE
488.2 with the associated standard event status enable (ESE) mask register, and from the registers
STATus:OPERation and STATus:QUEStionable which are defined by SCPI and contain detailed infor-
mation on the instrument.
The status reporting system further comprises the IST flag ("Individual STatus") with the parallel poll
enable (PPE) register allocated to it. The IST flag, like the SRQ, combines the entire instrument state in
a single bit. The function fulfilled by the PPE register for the IST flag corresponds to that fulfilled by the
SRE for the service request.
The output buffer contains the messages the instrument returns to the controller. The output buffer is
not part of the status reporting system but determines the value of the MAV bit in the STB register and is
therefore shown in Fig. 5-4.
Structure of an SCPI Status Register
Each SCPI register consists of five parts each of 16 bits width which have different functions (see Fig.
5-3). The individual bits are independent of each other, ie each hardware status is assigned a bit
number which is valid for all five parts. For example, bit 3 of the STATus:OPERation register is assigned
to the hardware status "Wait for trigger" for all five parts. Bit 15 (the most significant bit) is set to zero for
all five parts. This allows the controller to process the contents of the register parts as positive integer.
15 14 13 12 PTRansition part 3 2 1 0
15 14 13 12 EVENt part 3 2 1 0
15 14 13 12 ENABle part 3 2 1 0
& & & & & & & & & & & & & & & &
to higher-order register
Sum bit
& = logical AND
= logical OR
of all bits
+
+
15 14 13 12 NTRansition part 3 2 1 0
15 14 13 12 CONDition part 3 2 1 0
Fig. 5-3 Status register model