3. Serial RapidIO Electrical Interface > Port Aggregation: 1x and 4x Modes
68
Tsi574 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
The MACs are numbered by even numbers and support the ports in the following manner: serial ports
0 and 1 use MAC 0, ports 2 and 3 use MAC 2, etc. Ports are grouped into pairs of N and N+1, where N
is even.
Two configurations are possible on each 4x mode-capable port:
•
Both port N and port N+1 can operate in 1x mode (the 1x + 1x configuration)
•
Port N can operate in 4x while port N+1 is unused and can be powered down (the 4x + 0x
configuration)
Each Tsi574 MAC has an external pin called SPx_MODESEL. This pin can be pulled high to configure
the MAC for either 1x + 1x mode or pulled low for 4x + 0x mode (see
). These
pins are sampled after reset is de-asserted. To ensure that the pins are sampled correctly, the pins must
be stable at the release of reset, and held at a stable level for 10 clock cycles after reset is de-asserted.
The sampled state of the pins is reflected in the PORT_WIDTH field in the
After reset, the configuration mode can be re-programmed by changing the MAC_MODE field in the
“SRIO MAC x Digital Loopback and Clock Selection Register” on page 369
and the programmed
value overrides the pin setting of SPx_MODESEL. Changes to the MAC_MODE field that are
different than that set by the SPx_MODESEL pin must be programmed after a hardware or software
reset with a register write in order to restore the desired condition.
The PWRDNx4 and PWRDNx1 bits must both be asserted prior to changing the state of the
MAC_MODE bit. Therefore, changing the MAC operation from x4 to two x1 or from two x1 to x4
operation requires that the ports both be powered down using the PWRDNx4 and PWRDNx1 bits, and
then powered back up with the new setting of the MAC_MODE bit.
The port width in use can be different from the pin-selected width; the pin indicates what the port was
set to operate at, while the registers show what it is actually operating at. An even port with the
capability to function in either 1x or 4x mode port can be downgraded to a 1x mode port when faults on
lanes prevent operation in 4x mode. Additionally, the port width can be overridden through register
programming and changed into operating at a different port mode. Refer to
for status and control fields for port width and
for downgraded port configuration.
3.3.1
1x + 1x Configuration
When the 4x mode-capable port in a Tsi574 MAC is configured to operate in 1x mode, the
odd-numbered port in a MAC can also be used in 1x mode. In this configuration, the even-numbered
port always uses SerDes lane A and the odd-numbered port always uses SerDes lane B.
Ti
p
1x mode
means that one physical SerDes lane is used between link partners, and
4x mode
means that four physical lanes are used between link partners. 4x mode offers four times the
bandwidth as 1x mode at the same baud rate.
A port’s operation is not affected if the SPx_MODESEL signal values are changed after they
have been sampled at reset release.
Содержание IDT Tsi574
Страница 1: ...IDT Tsi574 Serial RapidIO Switch User Manual June 6 2016 Titl...
Страница 20: ...About this Document 20 Tsi574 User Manual June 6 2016 Integrated Device Technology www idt com...
Страница 34: ...1 Functional Overview JTAG Interface 34 Tsi574 User Manual June 6 2016 Integrated Device Technology www idt com...
Страница 100: ...4 Internal Switching Fabric Packet Queuing 100 Tsi574 User Manual June 6 2016 Integrated Device Technology www idt com...
Страница 224: ...11 Signals Pinlist and Ballmap 224 Tsi574 User Manual June 6 2016 Integrated Device Technology www idt com...
Страница 490: ...B Clocking P_CLK Programming 490 Tsi574 User Manual June 6 2016 Integrated Device Technology www idt com...
Страница 512: ...Index 512 Tsi574 User Manual June 6 2016 Integrated Device Technology www idt com...