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12. Serial RapidIO Registers > RapidIO Logical Layer and Transport Layer Registers 254
Tsi574 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
12.5.14 RapidIO Route Configuration Output Port CSR
This register and “RapidIO Route Configuration DestID CSR” on page 253 operate together to provide
indirect read and write access to the LUTs.
Writes to the LUTs through these registers affect the LUTs of all ports on the device. Reads from these
registers always return the data from Port 0.
This register set is identical to “RapidIO Port x Route Config DestID CSR” on page 306 (Offset 10070)
and “RapidIO Port x Route Config Output Port CSR” on page 307 (Offset 10074), except that
“RapidIO Port x Route Config Output Port CSR” on page 307 are per-port configuration registers and
they include an auto-increment bit to increment the contents of SPx_ROUTE_CFG_DESTID after a
read or write operation.
For details on how to configure the LUTs using this register, refer to “Lookup Tables” on page 37 .
Register name: RIO_ROUTE_CFG_PORT
Reset value: Undefined
Register offset: 0074
Bits 0 1 2 3 4 5 6 7
00:07 Reserved
08:15 Reserved
16:23 Reserved
24:31 PORT
Bits Name Description Type
Reset
Value
0:23 Reserved Reserved R 0
24:31 PORT Port
This is the RapidIO output port through which all reads and writes meant
for the CFG_DEST_ID field in the
“RapidIO Route Configuration DestID
CSR” on page 253 are sent.
Writing a value greater to this field than the PORT_TOTAL field in the
“RapidIO Switch Port Information CAR” on page 245 sets the LUT entry
to an unmapped state. For future compatibility, write the value 0xFF to
indicate an unmapped destination ID.
When reading an unmapped value from the LUT, this field is set to 0xFF.
R/W Undefined