Renesas IDT Tsi574, Руководство пользователя

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8. Performance > Congestion Detection and Management 197
Tsi574 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
— Threshold (THRESH): This field sets the threshold of how many times the ISF can re-order
packets before the INB_RDR bit in the RIO Port x Interrupt Status register is set.
The receiver versions of the registers contain the same fields as the registers related to the transmitters
however the receiver registers pertain to the ingress buffer queue status.
• “RapidIO Port x Receiver Input Queue Depth Threshold Register” on page 347
• “RapidIO Port x Receiver Input Queue Congestion Period Register” on page 351
• “RapidIO Port x Receiver Input Queue Congestion Status Register” on page 349
8.5.1.1 Interrupts
Each port's congestion management register set has two status interrupts, one for the ingress queue
depth status and one for the egress queue status.
Both interrupts are located in the “RapidIO Port x
Interrupt Status Register” on page 318 for the port.
The Congestion Counter and Congestion Period Counter fields must be polled in order to determine the
current congestion trend if waiting for the interrupts to occur is insufficient warning that the buffers in
the switch have become congested. Also, by tracking the Congestion Counter value and the Congestion
Period Counter value, it is possible to determine the traffic trend for the buffer.
8.5.1.2 Example of Congestion Register Behavior
In this example, the number of packets in the egress queue are monitored. The bursting ability of the
queue is shown with the frequent increase and decrease of packets. When the queue appears flat it
indicates either condition where the number of packets entering the queue is the same as the number of
packets leaving the queue appear in this manner or that queue was stalled during that period.
Figure 43 on page 198 is an example of what the congestion registers may contain at various times
during port operation.