Renesas F-ZTAT H8 Series, Руководство по оборудованию

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10. Serial Communication Interface
Rev.3.00 Jul. 19, 2007 page 309 of 532
REJ09B0397-0300
Communica-
tion line
RDRF
RDR
Frame 1 Frame 2 Frame 3
Data 1 Data 2 Data 3
Data 1 Data 2
RDR read RDR read
At A , data 1 is read.
At B , data 2 is read.
A B
Figure 10.26 Relationship between Data and RDR Read Timing
To avoid the situation described above, after RDRF is confirmed to be 1, RDR should only be read
once and should not be read twice or more.
When the same data must be read more than once, the data read the first time should be copied to
RAM, for example, and the copied data should be used. An alternative is to read RDR but leave a
safe margin of time before reception of the next frame is completed. Specifically, reading of RDR
should be completed before bit 7 is transferred in synchronous mode, or before the stop bit is
transferred in asynchronous mode.
Caution on Switching of SCK
3
Function: If pin SCK
3
is used as a clock output pin by SCI3 in
synchronous mode and is then switched to a general input/output pin (a pin with a different
function), the pin outputs a low level signal for half a system clock (
φ
) cycle immediately after it is
switched.
This can be prevented by either of the following methods according to the situation.
1. When an SCK
3
function is switched from clock output to non clock-output
When stopping data transfer, issue one instruction to clear bits TE and RE in SCR3 to 0 and to
set bits CKE1 and CKE0 to 1 and 0, respectively. In this case, bit COM in SMR should be left
1. The above prevents SCK
3
from being used as a general input/output pin. To avoid an
intermediate level of voltage from being applied to SCK
3
, the line connected to SCK
3
should be
pulled up to the V
CC
level via a resistor, or supplied with output from an external device.