Renesas F-ZTAT H8 Series, Руководство по оборудованию

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4. Clock Pulse Generators
Rev.3.00 Jul. 19, 2007 page 93 of 532
REJ09B0397-0300
Section 4 Clock Pulse Generators
4.1 Overview
Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a
system clock pulse generator and a subclock pulse generator. The system clock pulse generator
consists of a system clock oscillator and system clock dividers. The subclock pulse generator
consists of a subclock oscillator circuit and a subclock divider.
4.1.1 Block Diagram
Figure 4.1 shows a block diagram of the clock pulse generators.
System clock
oscillator
System clock
divider (1/2)
φ
φ
φ
φ
φ
φ
φ
φ
φ
φ
φ
Subclock
oscillator
Subclock
divider
(1/2, 1/4, 1/8)
System clock
divider (1/8)
System clock pulse generator
Subclock pulse generator
Prescaler S
(13 bits)
Prescaler W
(5 bits)
OSC
OSC
1
2
X
X
1
2
OSC
(f )
OSC
W
(f )
W
/2
OSC
/2
W
/8
W
SUB
/2
to
φ
/8192
φ
/2
W
φ
/4
W
φ
/8
to
φ
/128
W
W
/16
OSC
/4
W
W
Figure 4.1 Block Diagram of Clock Pulse Generators
4.1.2 System Clock and Subclock
The basic clock signals that drive the CPU and on-chip peripheral modules are
φ
and
φ
SUB
. Four of
the clock signals have names:
φ
is the system clock,
φ
SUB
is the subclock,
φ
OSC
is the oscillator
clock, and
φ
W
is the watch clock.