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Rabbit 6000 User’s Manual
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47
4.3.3 Watchdog Timer
The watchdog timer is enabled on reset with a 2-second timeout. Unless specific data are written to
WDTCR before that time expires, the processor will be reset. The watchdog timer can be disabled by writ-
ing a sequence of two bytes to WDTTR as described in the register description.
The watchdog timer also contains a special test mode that speeds up the timeout period by clocking it with
the peripheral clock instead of the 32 kHz clock. This mode can be enabled by writing to WDTTR.
4.3.4 Secondary Watchdog Timer
The secondary watchdog timer is disabled on reset. The following steps explain how to use the secondary
watchdog timer.
1. Write the vector to the interrupt service routine to the internal interrupt table.
2. Write the desired timeout period to SWDTR. This also enables the secondary watchdog timer.
3. Restart the secondary watchdog timer by either writing the timeout period to SWDTR or writing
0x5F to WDTCR.
If the secondary watchdog timer counts down to zero, a Priority 3 secondary watchdog interrupt will occur.
This interrupt request is cleared by writing a new timeout value to SWDTR. A sample interrupt handler is
shown below.
secwd_isr::
push af
; determine why the interrupt occurred and take appropriate
action
ld a, 0x40 ; timeout period of 0x40/32kHz = 1.95ms
ioi ld (SWDTR), a ; clear the interrupt request
pop af
ipres
ret
4.3.5 CPU Clock Cycle Counter
This counter counts the number of CPU cycles that occur during one 32 kHz clock period. The least signif-
icant 8 bits of this 14-bit counter are accessed by reading WDTCR, and the upper 6 bits are accessed by
reading WDTTR. This value is updated continually, so be careful to not change the main clock frequency
between reading the two registers.
Table 4-1. Watchdog Timer Settings
WDTCR Value
Effect
0x5A
Restart watchdog timer with 2-second timeout.
0x57
Restart watchdog timer with 1-second timeout.
0x59
Restart watchdog timer with 500-millisecond timeout.
0x53
Restart watchdog timer with 250-millisecond timeout.
0x5F
Restart the secondary watchdog timer.
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