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Rabbit 6000 User’s Manual
digi.com
113
11. P
ARALLEL
P
ORT
D
11.1 Overview
Parallel Port D is a byte-wide port with each bit programmable for data direction and drive level. These are
simple inputs and outputs controlled and reported in the Port D Data Register (PDDR).
All of the Parallel Port D pins have alternate output functions, and all of them can be used as inputs to var-
ious on-chip peripherals.
When used as simple digital outputs, the Parallel Port D bits are buffered, with the data written to PDDR
transferred to the output pins on a selected timing edge. Either the peripheral clock or the outputs of Timer
A1, Timer B1, or Timer B2 can be used for this function, with each nibble of the port having a separate
select field to control this timing. Each bit can either be programmed as open-drain or driven high and low.
Because of the buffered nature of Parallel Port D, a read-modify-write type of operation can lead to old
data being written to PDDR. To alleviate this potential problem, each bit of the port can be written individ-
ually using a separate address for each bit.
The drive strength and slew rate can be individually controlled for each Parallel Port D pin. In addition, a
75 k
pullup or pulldown resistor can be enabled on each pin.
Note that it is possible for either Flexible Interface Module to use any of the parallel ports. See Chapter 33
for more information.
NOTE:
IA6 and IA7 are address bits for External I/O.
Table 11-1. Parallel Port D Pin Alternate Output Functions
Pin Name
Alt Out 0
Alt Out 1
Alt Out 2
Alt Out 3
PD7
IA7
I7
PWM3
SCLKC
PD6
TXA
I6
PWM2
TXE
PD5
IA6
I5
PWM1
RCLKE
PD4
TXB
I4
PWM0
TCLKE
PD3
IA7
I3
TIMER C3
SCLKD
PD2
SCLKC
I2
TIMER C2
TXF
PD1
IA6
I1
TIMER C1
RCLKF
PD0
SCLKD
I0
TIMER C0
TCLKF
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