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Rabbit 6000 User’s Manual
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256
24.3 Operation
It is possible to set up and start a DMA operation by writing directly to all the relevant address, length, and
control registers, but it is expected that the typical operation would be to create a buffer descriptor in mem-
ory, write the address of that descriptor to the initial address registers (DyIAnR), and use a write to DMALR
to auto-load the values from memory into the registers and start the transfer. The DMA transfer will then
continue reading buffer descriptors until a buffer-marked halt is completed.
The descriptor can be either 12 or 16 bytes in length; a bit in the channel control byte (which corresponds to
DyCR) selects whether the link address is present or not. The processor skips the read of those bytes if a
12-byte descriptor is selected, and always skips the reads of the bytes marked “not used.”
Note that a length value of 0x0000 will result in a 65536-byte transfer.
The C structure to hold a descriptor is shown below.
typedef struct {
char frameStatus; // DxSCR
char chanControl; // DxCR
unsigned int bufLength; // DxL0R, DxL1R
dma_addr_t srcAddress; // DxSA0R, DxSA1R, DxSA2R
dma_addr_t destAddress; // DxDA0R, DxDA1R, DxDA2R
dma_addr_t linkAddress; // DxLA0R, DxLA1R, DxLA2R
} DMABufDesc;
It is possible to abort a DMA transfer by writing the appropriate bit to the halt register,
DMHLR/DMHMR. It is also possible to restart a DMA transfer using the already-loaded register values
by writing to DMCSLR/DMCSHR.
The following steps explain how to set up a DMA channel.
1. Select the DMA transfer and interrupt priorities by writing to DMCR.
2. Select the DMA channel priority and maximum burst size by writing to DCSTCR. If not using the
bus-interleaving mode, use DMTCR instead and include the minimum clocks between bursts as
well.
3. If using an interrupt, write the interrupt vector for the interrupt service routine to the external inter-
rupt table.
4. If using an external DMA request, enable an external request line by writing to DMR0CR or
DMR1CR. Make sure that the pin selected is set up as an input. Note that this enable will be logi-
cal-ANDed to any internal DMA enables if the DMA transfer is to/from an internal peripheral.
Table 24-2. DMA Buffer Descriptor
Byte 0
Byte 1
Byte 2
Byte 3
Bytes 0–3
Special Channel
Control /
Frame Status
Channel Control
Buffer Length [15:0]
Bytes 4–7
Source Address [23:0]
Not Used
Bytes 8–11
Destination Address [23:0]
Not Used
Bytes 12–15
Link Address [23:0]
Not Used
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