PLX Technology PEX 8680, Руководство по конструкции аппаратуры

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PEX 8680 Quick Start Hardware Design Guide, Version 1.1
© 2011 PLX Technology, Inc. All Rights Reserved.
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Figures
Figure 1. Sample PCI Express Link Block Diagram ..................................................................................... 1
Figure 2. Single-Ended versus Differential Voltage ...................................................................................... 2
Figure 3. Transport Delay Delta ................................................................................................................... 5
Figure 4. PEX 8680 RefClk Circuit ............................................................................................................... 5
Figure 5. Top Layer BGA Layout and Routing Escape ................................................................................ 7
Figure 6. Bottom Layer BGA Layout, Escape, and De-coupling Capacitor Placement
............................... 7
Figure 7. Add-In Card Routing to PCI Express Gold Fingers ....................................................................... 8
Figure 8. System Board Routing to PCI Express Slot .................................................................................. 8
Figure 9. PCI Express Midbus Routing Example ......................................................................................... 9
Figure 10. Enable NT Function with NT Strapping Balls ............................................................................ 10
Figure 11. Disable NT Function .................................................................................................................. 10
Figure 12. I
2
C Interface Block Diagram ...................................................................................................... 11
Figure 13. PHPC Circuit Block Diagram ..................................................................................................... 12
Figure 14. SHPC Interface to PEX 8680 Block Diagram ........................................................................... 13
Figure 15. JTAG Interface Block Diagram .................................................................................................. 14
Tables
Table 1. Receiver Equalization Settings ....................................................................................................... 4
Table 2. PEX 8680 LED On/Off Patterns, by State .................................................................................... 14
Table 3. Cross-Reference of Ball Names and Related Debug Signal Names ........................................... 15
Table 4. Configuration Strapping Balls ....................................................................................................... 17