PEX 8680 Quick Start Hardware Design Guide, Version 1.1
© 2011 PLX Technology, Inc. All Rights Reserved.
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11.1 Power Supplies
The PEX 8680 has the following Power ball groups:
VDD10 – Digital core logic supply
VDD10A – SerDes analog supply
VDD25 – Hot Plug, serial EEPROM, I
2
VDD25A – PEX_REFCLK PLL supply
C, JTAG, Port Status indicators, I/O buffers
At the board level, VDD10 and VDD10A can share a common 1.0V ±5% power plane, and VDD25 and
VDD25A can share a common 2.5V power plane. The current demands for these supplies can be high,
depending upon the device (approximately 80 mA per Lane, plus 32 mA); therefore, ensure that the
power plane is sufficiently sized, to support the specified operating current. For best performance, the
1.0V ±5% plane should have an adjacent ground plane that provides an interplane capacitor to supply
high-frequency transient currents. Provide a sufficient number of discrete capacitors for mid- and
low-frequency de-coupling. The recommendation is that 0201-sized capacitors be used in close proximity
to these power balls.
VDD10A has a lower noise tolerance than the digital supplies. Therefore, VDD10A might require
additional filtering, depending upon the 1.0V ±5% power plane noise. The SerDes can tolerate ±5%
variance on the supply rails, due to noise and IR drop. VDD25 power is used for the single-ended I/O
buffers – Hot Plug, serial EEPROM, JTAG, I
2
11.2 Power Sequencing
C, and the Port Status indicators. Although power
consumption for this supply is relatively small, the output drivers have fast edge rates, and therefore,
require that adequate power de-coupling be provided, to supply transient current to the drivers. It is
preferred that VDD25 be implemented as a plane or partial plane, either on a signal layer or main power
plane layer. Provide 0.1 and/or 0.01 µF ceramic capacitors, along with one or more 10-µF tantalum
capacitors, to de-couple the VDD25 power balls. The number of capacitors required depends upon the
number of 2.5V I/O balls utilized in the design, and the existence or absence of an interplane capacitance
for the VDD25 rail.
There is no power sequencing requirement.
11.3 Board-Level De-Coupling
Board-level de-coupling requirements for high-speed digital designs are highly dependent upon several
factors, including:
Printed circuit board (PCB) layer stack-up
Differential versus single-ended I/O signaling
Driver edge rates
Number of I/Os utilized
and numerous other factors. For this reason, it is not possible to present a generalized de-coupling
solution that will work for all designs.
Board-level power supply de-coupling exists primarily in two forms:
Parallel plane capacitance
Use of discrete capacitors
