PEX 8680 Quick Start Hardware Design Guide, Version 1.1
© 2011 PLX Technology, Inc. All Rights Reserved.
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PEX 8680
SDA
SCL
INT#
16/40 I/O Expander
MAX7311 or
PCA9698
Interlock
Sltid[4:0]
GPIO
AD[2:0]
I
2
C
Port 1
PCI
Express
Slot
VCC
System
Power
Supply
12V, 3.3V
VCC
VCC
VCC
VCC
Hot Plug
Controller
FETs
Clock
Buffer
Clken#
Atnled#
Pwrled#
Pwren
Perst#
Button#
Pwrflt#
Mrl#
Prsnt#
Pwrgood
VCC
VCC
4
3
IO 13/29
IO 11/17
IO 0/16
IO 2/18
IO 3/19
IO 14/30
IO 5/21
IO 6
IO[10:7]/[26:22]
IO 11/27
IO 12/28
IO 15/31
VCC
VCC
GPIO
VCC
Figure 14. SHPC Interface to PEX 8680 Block Diagram
6
JTAG Interface
The PEX 8680 supports a five-ball JTAG Boundary Scan interface. The JTAG interface consists of the
following signals:
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST#
At the board level, pull JTAG_TDI, JTAG_TMS, and JTAG_TCK up to 2.5V with 1-kohm to 5-kohm
resistors. Pull JTAG_TRST# down to VSS with a 1-kohm to 5-kohm resistor. Because the PEX 8680
JTAG clock frequency can be as high as 10 MHz, a 15-ohm series terminator can be added to TCK, TDI,
and TDO, to improve signal quality.
