PLX Technology PEX 8680, Руководство по конструкции аппаратуры

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PEX 8680 Quick Start Hardware Design Guide, Version 1.1
© 2011 PLX Technology, Inc. All Rights Reserved.
5
In PCI Express, the cut-off frequency of the PLL is specified to be between 1.5 to 22 MHz for 2.5 GT/s
and 8 to 16 MHz for 5.0 GT/s data rates. The purpose of these bandwidth ranges is to limit the difference
in PLL bandwidth on the two sides of a Link. This is especially important for common clock systems,
where the amount of jitter appearing at the CDR is defined by the difference function between the Tx and
Rx PLLs.
Another mechanism that can increase jitter seen by a Receiver in common clocked systems is the fixed
phase difference (transport delay delta) between Transmitter data at the CDR input and a Receiver’s
recovered clock, relative to the 100-MHz Reference Clock source. This delay should not exceed 12 ns
per PCI Express specification. The delay budget includes on-chip and off-chip delays. In general terms,
all Reference Clock nets in a system should be matched within 38.1 cm (15 in.).
Figure 3 illustrates the
Reference Clock transport delay delta.
The PEX 8680 PEX_REFCLKn/p signal is the Reference Clock Input buffer. It has an internal DC-biasing
circuit, and hence, should be AC-coupled from the RefClk source driver. Use 0.01 to 0.1 µF capacitors
(0603 or 0402-size) to AC-couple the Reference Clock input, as illustrated in
Figure 4 .
PLL1
CDR1
PLL2
CDR2
RefClk
Rx1
Rx2 Tx1
Tx2
Channel
Channel
Device 1 Device 2
T1
T2
T3
T4
T5
Transport Delay Delta = (T1+T2+T3) – (T4+T5) < 12 ns
Figure 3. Transport Delay Delta
33 ohm
33 ohm
49.9 ohm
0.1 µF
PEX 8680
PCI Express
RefClk Driver
PEX_REFCLKp
PEX_REFCLKn
Source termination placed close to driver .
49.9 ohm
0.1 µF
Place AC-coupling capacitors
near PEX_REFCLKn/p balls
Figure 4. PEX 8680 RefClk Circuit