Development Board for phyCORE-PXA255
PHYTEC Meßtechnik GmbH 2004 L-657e_0
Table 12: PLD U6 Control Register 5 ......................................................... 25
Table 13: PLD U6 Control Registers 6 and 7.............................................. 25
Table 14: PLD U6 Control Register 8 ......................................................... 26
Table 15: PLD U6 Control Register 9 ......................................................... 27
Table 16: PLD U6 Control Register 10 ....................................................... 27
Table 17: PLD U6 Control Register 11 ....................................................... 28
Table 18: IDE Control Register with Reset Values..................................... 32
Table 19: IDE Control Register 0................................................................ 32
Table 20: IDE Control Register 1................................................................ 33
Table 22: IDE Control Register 3................................................................ 34
Table 23: IDE Control Register 4................................................................ 34
Table 24: TrueIDE Memory Area Assignment ........................................... 35
Table 25: Physical Address Range of the IDE Interface ............................. 35
Table 26: CF Card Control Register with Reset Values.............................. 37
Table 27: CF Card Control Register 0......................................................... 37
Table 28: CF Card Control Register 1......................................................... 38
Table 29: CF Card Control Register 2......................................................... 38
Table 30: CF Card Control Register 3......................................................... 39
Table 31: CF Card Control Register 4......................................................... 39
Table 32: CF Card Control Register 5......................................................... 40
Table 33: CF Card Control Register 6......................................................... 40
Table 34: Address Space for Ethernet Controller........................................ 42
Table 35: USB Host Jumpers ...................................................................... 44
Table 36: LCD Connector at X33 ............................................................... 48
Table 37: BT-UART Jumper Configuration ............................................... 52
Table 38: IR-UART Connector at X19 ....................................................... 53
Table 39: IR-UART Jumper Configuration ................................................ 53
Table 40: CAN Interface Jumper Configuration ......................................... 56
Содержание phyCORE-PXA255
Страница 8: ...Development Board for phyCORE PXA255 PHYTEC Me technik GmbH 2004 L 657e_0...
Страница 20: ...Development Board for phyCORE PXA255 12 PHYTEC Me technik GmbH 2004 L 657e_0...
Страница 26: ...Development Board for phyCORE PXA255 18 PHYTEC Me technik GmbH 2004 L 657e_0...
Страница 54: ...Development Board for phyCORE PXA255 46 PHYTEC Me technik GmbH 2004 L 657e_0...
Страница 62: ...Development Board for phyCORE PXA255 54 PHYTEC Me technik GmbH 2004 L 657e_0...
Страница 72: ...Development Board for phyCORE PXA255 64 PHYTEC Me technik GmbH 2004 L 657e_0...
Страница 76: ...Development Board for phyCORE PXA255 68 PHYTEC Me technik GmbH 2004 L 657e_0...
Страница 94: ...Development Board for phyCORE PXA255 86 PHYTEC Me technik GmbH 2004 L 657e_0...
Страница 98: ...Development Board for phyCORE PXA255 90 PHYTEC Me technik GmbH 2004 L 657e_0...
Страница 101: ...Appendices PHYTEC Me technik GmbH 2004 L 657e_0 93 Appendices A AI Hardware Revision...
Страница 102: ...Development Board for phyCORE PXA255 94 PHYTEC Me technik GmbH 2004 L 657e_0...
Страница 106: ...Published by PHYTEC Me technik GmbH 2004 Ordering No L 657e_0 Printed in Germany...