Development Board for phyCORE-PXA255
44
PHYTEC Meßtechnik GmbH 2004 L-657e_0
The following table gives an overview of jumpers relevant for
configuring the USB interface:
Jumper
Default Comment
JP3
This jumper configures the USB controller OTG ID
input. Refer to ISP1362 USB-OTG controller data sheet
and user’s manual for details.
1 + 2
-
OTG ID = 10 kOhm pull-up,for external OTG ID signal
OTG ID tied to Ground.
2 + 3
X
JP5
This jumper configures the USB controller VDD_5V
input. Refer to ISP1362 USB-OTG controller data sheet
and user’s manual for details.
1 + 2
-
OTG_5V connected to 3.3V (VDD_5V pin on ISP1362)
2 + 3
X
OTG_5V connected to 5V (VDD_5V pin on ISP1362)
JP6
This jumper configures the routing of the first USB
channel supply voltage. Refer to ISP1362 USB-OTG
controller data sheet and user’s manual for details.
1 + 2
-
USB 5V routed to OTG interface on expansion board.
2 + 3
X
USB 5V routed to USB host interface on development
board.
JP9
This jumper configures reference voltage for the OTG
interface. Refer to ISP1362 USB-OTG controller data
sheet and user’s manual for details.
1 + 2
-
OTG_VBUS connected to USB 5V from interface #1
OTG_VBUS open
2 + 3
X
Table 35:
USB Host Jumpers
Содержание phyCORE-PXA255
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