Phytec phyCORE-PXA255, Руководство по оборудованию

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Development Board for phyCORE-PXA255
22 
PHYTEC Meßtechnik GmbH 2004 L-657e_0
REG ADDR. D7-D4 D3 D2 D1 D0
CTRL0
0x0c000000 Res Res GPIO0 RESOUT SRES
RESET 0 0 0
CTRL 1
0x0c000002 Res PM_5V CANPWR Res 5V_OFF
RESET X 0 0
CTRL 2
0x0c000004 Res Res LEDBAS LEDUSR LEDPWR
RESET 0 0 0
CTRL 3
0x0c000006 Res POS1 POS2 LCDON LCDPWR
RESET 0 0 0 0
CTRL 4
0x0c000008 Res Res Res Res MMC1PWR
RESET 0
CTRL 5
0x0c00000A Res WP DET LED MMC2PWR
RESET
CTRL 6
0x0c00000C Res INT3 INT2 INT1 INT0
RESET 0 0 0 0
CTRL 7 0x0c00000E Res INT
PM_5V INT
MMCDET INT
FF_RI INT
BT_DET
RESET 0 0 0 0
CTRL 8
0x0c000010 Res BT_Rx FF_RI BT_SD FF_SD
RESET 0 0
CTRL 9
0x0c000012 Res Res AC97 ENA /FL_DIS FL_WP
RESET 0 0 1
CTRL 10
0x0c000014 Res Res Res Res Res
RESET
CTRL 11
0x0c000016 Res ALARM ACPRES ACSEL ACENA
RESET 0 0
Table 6: Control PLD U6 Reset Values
The reset properties for RES_DEV on the Development Board are set
in control register 0. RES_DEV is the reset signal that only affects the
USB, CAN and Ethernet controller of the phyCORE-PXA255.
Therefore it is possible to use the RESETOUT of the PXA255
controller in watchdog mode without having to reinitialize these
controllers.
REG ADDR D7-D4 D3 D2 D1 D0
CTRL0 0x0c000000 Res Res GPIO0 RESOUT SRES
RW R/W=0 R/W=0 R/W R/W R/W
Table 7: PLD U6 Control Register 0
SRES Setting this bit generates a system reset.
RESOUT If this bit is set and RESETOUT = 0 on the
PXA255, then a RES_DEV will be generated.
GPIO0 If this bit is set and GPIO0 = 0 on the PXA255,
then a RES_DEV will be generated.