Phytec phyCORE-PXA255, Руководство по оборудованию

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Memory Configuration
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PHYTEC Meßtechnik GmbH 2004 L-657e_0
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IDE control register 1 is used to set the memory interface and the
DMA access. Since a hard drive only supports the TruIDE mode of a
CF card interface, this has a fixed setting in register bit 0. The
PXA255 controller’s PCMCIA interface does not support TruIDE
mode. Therefore the /IDE_PCE1 signal is linked with A11='0' and the
/IDE_PCE2 signal is linked with A11='1'. Both signals are active
during 8-bit as well as 16-bit accesses. As an option the IDE interface
can also run in DMA mode. The DMA mode is activated by setting
DMAENA. The free DMA channel can be selected in register
DMA0/1. The DACK signal is generated if A21=1 and A13=0.
REG ADDR D7 D3 D2 D1 D0
IDE 1 0x2001002 Res DMA0/1 DMAEN RES IDE/MEM
RW
R/W=0 R/W R/W R/W=0 R=1/W=1
Table 20: IDE Control Register 1
IDE/MEM Setting this bit to "1" selects the TrueIDE mode. In
this mode address line A11 is used to switch the
PCE1 and PCE2 memory areas. It is not possible to
use the memory mode.
DMAEN This bit enables the optional DMA mode.
DMA0/1 This bit configures the available DMA channel.
IDE control register 2 includes the control signals for Reset and
Ready. The hard drive reset can be controlled via software. Bit 1 of
the IDE control register 2 will generate a reset if set to "0" while
setting this bit to "1" will end the reset cycle. Reading bit 3 returns the
status of the hard drive RDY signal.
REG ADDR D7 D3 D2 D1 D0
IDE 2 0x2001004 Res RDY Res /IDE_RES Res
RW
R RW
Table 21: IDE Register 2
/IDE_RES Low active reset signal for the hard drive.
/RDY Shows current state of the hard drive Ready signal.