Phytec phyCORE-PXA255, Руководство по оборудованию

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Development Board for phyCORE-PXA255
26 
PHYTEC Meßtechnik GmbH 2004 L-657e_0
INT0 IRQ status bit for BT-UART detect
INT1 IRQ status bit for FF-UART detect
INT2 IRQ status bit for MMC-Card 2 detect
INT3 IRQ status bit for 5 V power not present
Clear bit = interrrupt active if one of the four bit = 0 => /INT0-BIT
INT_BT_DET Enable bit for BT-UART detect
INT_FF_DET Enable bit for FF-UART detect
INT_MMCDET Enable bit for MMC card 2 detect
INT_PM5V
Enable bit for 5 V power not present
Only if the corresponding bit is set to "1", then an interrupt will erase
the "clear bit" and hence release an interrupt.
Control register 8 controls the RS-232 transceiver for the BT/IR
UART and the FF-UART.
REG ADDR D7-D4 D3 D2 D1 D0
CTRL 8 0x0c000010 Res BT_Rx FF_RI BT_SD FF_SD
RW R/W=0 R R R/W R/W
Table 14: PLD U6 Control Register 8
FF-SD Setting this bit shuts down the RS-232 transceiver
for the FF-UART.
BT-SD Setting this bit shuts down the RS-232 transceiver
for the BT-UART and IR-UART.
FF_RI If the RS-232 transceiver for the FF-UART is in
power down mode then this bit returns an active RI
signal.
BT_Rx If the RS-232 transceiver for the BT-UART or
IR-UART is in power down mode then this bit
returns an active RxD signal.
The Flash device on the phyCORE module and the AC97 expansion
interface can be configured in control register 9. If /FL_DIS is set to
0, then it is possible to boot from an external Flash (not on the
phyCORE-PXA255).