Phytec phyCORE-P8xC51Mx2, Руководство по оборудованию

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phyCORE-P8xC51Mx2
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PHYTEC MMesstechnikGmbH 2005 L-602e_3
4.2 Control Register 2
Control Register 2 (Address 3F:FC01H/00:FC01H)
Bit 7 Bit 0
N/A
1
N/A N/A N/A IO_SW N/A N/A N/A
Default Values:
Reset Value:
Runtime Model:
0000 0000 b
0000 0000 b
Table 17: Control Register 2 of the Address Decoder
IO-SW: By means of this bit, the I/O area of the module can be
selectively mapped either to the upper or to the lower
64 kByte of the address space. With
IO-SW = 0 following a hardware reset, the I/O area is
accessible in the range between FC00H - FFFFH.
Setting bit IO-SW = 1 maps the I/O area to
3F:FC00H – 3F:FFFFH.
This I/O area generally consists of 4 blocks of
256 bytes each. In three of these blocks, the address
decoder provides a pre-decoded Chip Select signal that
simplifies the connection of peripheral hardware to the
module.
These Chip Select signals will be activated on
read/write access to the XDATA memory space within
the appropriate address range. The fourth block is
reserved for internal access to the decoder’s internal
register (write-only access). This block is not available
for use of connecting external devices.
1
: N/A: Not Accessible