Phytec phyCORE-P8xC51Mx2, Руководство по оборудованию

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phyCORE-P8xC51Mx2
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PHYTEC MMesstechnikGmbH 2005 L-602e_3
The following figure illustrates the default memory model:
0 8 0 0 0 0 H
2 0 0 0 0 0 H
3 F F F F F H
0 C 0 0 0 0 H
0 4 0 0 0 0 H
0 0 0 0 0 0 H
C O D E D A T A
M e m o r y P 8 x C 5 1 M x 2
2 M B F L A S H
1 M B F L A S H
5 1 2 k B F L A S H
2 5 6 k B F L A S H
F l a s h T o o l s - F i r m w a r e 3 2 k B
F l a s h U 7 ( / C S F l a s h )
1 2 8 k B S R A M
1 0 : 0 0 0 0 H
1 2 8 k B S R A M
1 2 8 k B S R A M
U 6
U 5
5 1 2 k B S R A M
U 6
5 1 2 k B S R A M
U 5
1 2 8 k B S R A M
U 6
U 5
R A M - S W = 1 R A M - S W = 0
I O
I O
I O - S W = 0
C S 3 0 0 : F F 0 0 h - 0 0 : F F F F h
C S 2 0 0 : F E 0 0 h - 0 0 : F E F F h
C S 1 0 0 : F D 0 0 h - 0 0 : F D F F h
C S R E G 0 0 : F C 0 0 h - 0 0 : F C F F h
I O - S W = 1
C S 3 3 F : F F 0 0 h - 3 F : F F F F h
C S 2 3 F : F E 0 0 h - 3 F : F E F F h
C S 1 3 F : F D 0 0 h - 3 F : F D F F h
C S R E G 3 F : F C 0 0 h - 3 F : F C F F h
Figure 8: Default Memory Model following a Hardware Reset
The following sections describe the address decoder’s registers for
configuration of the memory model.