Phytec phyCORE-OMAP44 Series, Руководство по оборудованию

Страница: 67 / 168

phyCORE-OMAP44xx Part I: PCM-049/phyCORE-OMAP44xx System on Module
L-760e_1 © PHYTEC Messtechnik GmbH 2012 55
1.8.7 SPI Interface
The Serial Peripheral Interface (SPI) interface is a four-wire, bidirectional synchronous serial bus that provides
a simple and efficient method for data exchange among devices. The multichannel serial port interfaces (McSPI)
of the OMAP44xx has four separate modules (SPI1, SPI2, SPI3, and SPI4). The interface signals of the first
module (McSPI1) are made available on the phyCORE-Connector. This module is Master/Slave configurable and
supports up to four peripherals. The following table lists the SPI signals on the phyCORE-Connector:
1.8.8 Multichannel Buffered Serial Port (McBSP)
The Multichannel Buffered Serial Port (McBSP) interface of the phyCORE-OMAP44xx is a full-duplex, serial port
that allows to communicate with a variety of serial devices in a system such as other application chips (digital
base band), audio and voice codecs,etc. The McBSP supports a direct interface to industry-standard codecs,
analog interface chips (AICs) and other serially connected A/D and D/A devices, such as Inter-IC sound (I
2
S)
compliant devices, pulse code modulation (PCM) devices and time devision multiplexed (TDM) bus devices.
The OMAP44xx controller offers four instances of the McBSP module. The interface signals of the third module
(McBSP3) are brought out to the phyCORE-Connector. The following table shows the location of the McBSP
signals on the phyCORE-Connector.
Pin # Signal I/O SL Description
X1A31 X_SPI1_CS0 I/O 1.8 V / VCC_1V8_IO McSPI1 chip select 0
(slave input, master output)
X1B31 X_SPI1_CS1 O VCC_1V8_IO McSPI1 chip select 1
X1B32 X_SPI1_CS2 O VCC_1V8_IO McSPI1 chip select 2
X1A33 X_SPI1_CS3 O VCC_1V8_IO McSPI1 chip select 3
X1B33 X_SPI1_MOSI I/O 1.8 V / VCC_1V8_IO McSPI1 master output /
slave input
X1A34 X_SPI1_MISO I/O 1.8 V / VCC_1V8_IO McSPI1 master input/
slave output
X1B34 X_SPI1_CLK I/O 1.8 V / VCC_1V8_IO McSPI1 clock master output/
slave input
Table 24: SPI Interface Signal Location
Pin # Signal I/O SL Description
X1B28 X_McBSP3_CLKX I/O 1.8 V / VCC_1V8_IO ABE McBSP3 combined
serial clock
X1A40 X_McBSP3_DX I/O 1.8 V / VCC_1V8_IO ABE McBSP3 transmitted
serial data
X1B41 X_McBSP3_FSX I/O 1.8 V / VCC_1V8_IO ABE McBSP3 combined
frame synchronization
X1B42 X_McBSP3_DR I 1.8 V ABE McBSP3 received serial
data
Table 25: McBSP Signal Location