Phytec phyCORE-OMAP44 Series, Руководство по оборудованию

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phyCORE-OMAP44xx Part I: PCM-049/phyCORE-OMAP44xx System on Module
L-760e_1 © PHYTEC Messtechnik GmbH 2012 59
1.10 Debug Interface (X7)
The phyCORE-OMAP44xx is equipped with a JTAG interface for downloading program code into the external
flash, internal controller RAM or for debugging programs currently executing. The JTAG interface extends to a
2.0 mm pitch pin header at X7 on the edge of the module PCB and also to the phyCORE-Connector X1.
Figure 9 and Figure 10 show the position of the debug interface (JTAG connector X7) on the phyCORE-OMAP44xx
module. Even numbered pins are on the top of the module, starting with 2 on the right to 20 on the left, while
odd number pins are on the bottom, starting from (as viewed from the top) 1 on the right to 19 on the left.
The JTAG edge card connector X7 provides an easy means of debugging the phyCORE-OMAP44xx in your target
system via an external JTAG probe.
Table 28 shows the pin assignment of the JTAG connector X7. The location of the JTAG signals on the
phyCORE-Connector X1 is shown in Table 29 .
PHYTEC offers a JTAG-Emulator adapter (order code JA-002) for connecting the phyCORE-OMAP44xx to a
standard emulator. The JTAG-Emulator adapter extends the signals of the module's JTAG connector to a
standard ARM connector with 2 mm pin pitch. The JA-002 therefore functions as an adapter for connecting the
module's non-ARM-compatible JTAG connector X7 to standard Emulator connectors.
Note:
The JTAG connector X7 only populates phyCORE-OMAP44xx modules with order code PCM-049-xxxxxxxJxx.
This version of the phyCORE module must be special ordered. The JTAG connector X7 is not populated on
phyCORE modules included in the Rapid Development Kit. All JTAG signals are accessible from the carrier
board. The JTAG signals are also accessible at the phyCORE-Connector X1 (Samtec connectors). We recom-
mend integration of a standard (2.54 mm pitch) pin header connector in the user target circuitry to allow easy
program updates via the JTAG interface. See
Table 29 for details on the JTAG signal pin assignment.
Signal Pin Row
1
1. Note: Row A is on the controller side of the module and Row B is on the connector side of the module
Signal
A B
VCC_1V8_IO 2 1 TREF (VCC_1V8_IO via 100 Ohm)
GND 4 3 X_JTAG_nTRST
GND 6 5 X_JTAG_TDI
GND 8 7 X_JTAG_TMS
GND 10 9 X_JTAG_TCK
GND 12 11 X_JTAG_RTCK
GND 14 13 X_JTAG_TDO
GND 16 15 X_nRESET_WARM
GND 18 17 X_DPM_EMU0
GND 20 19 X_DPM_EMU1
Table 28: JTAG Connector X7 Signal Assignment