Service Modes, Error Codes, and Fault Finding
5.
Figure 5-5 “Off” to “Semi Stand-by” flowchart (part 2)
No
EJTAG probe
connected ?
No
Yes
Bootscript ready
in 1250 ms?
Yes
No
Release AVC system reset
Feed warm boot script
Cold boot?
Yes
No
RPC start (comm. protocol)
Set I²C slave address
of Standby µP to (60h)
An EJTAG probe (e.g. WindPower ICE probe) can
be connected for Linux Kernel debugging purposes.
This is still the timing of the
Jaguar 2k6. Timing need to be
updated if more mature info is
available.
This is still the timing of the
Jaguar 2k6. Timing needs to
be updated if more mature info
Detect EJTAG debug probe
(pulling pin of the probe interface to
ground by inserting EJTAG probe)
Release AVC system reset
Feed cold boot script
Release AVC system reset
Feed initializing boot script
disable alive mechanism
No
Set I²C slave address
of Standby µP to (A0h)
Switch LOW the RESET-NVM_WP-NANDFLASH line. Add a 2ms delay
before trying to address the NVM to allow correct NVM initialization.
This will allow access to NVM and
NAND FLASH and can not be done
earlier because the FLASH needs to
be in Write Protect as long as the
supplies are not available.
Enable the supply fault detection
algorithm
Yes
SP
Standby line set to HIGH for 5
seconds
No
I_17960_062
b
.ep
s
2
3
050
8
Yes
MIPS reads the wake up reason
from standby µP.
3-th try?
Blink Code as
error code
SP
Enable Alive check mechanism
Wait until AVC starts to
communicate
SW initialization
succeeded
within 20s?
No
Switch Standby
I/O line high.
RPC start (comm. protocol)
Yes
Disable all supply related protections and
switch off the +2V5, +3V3 DC/DC converter.
switch off the remaining DC/DC
converters
Wait 5ms
Switch AVC PNX8541
in reset (active low)
Wait 10ms
Switch the NVM reset
line HIGH.
Flash to Ram image
transfer succeeded
within 30s?
No
Yes
Code = 53
Code = 5
This is still the timing of the
Jaguar 2k6. Timing needs to
be updated if more mature info
is available.
This is still the timing of the
Jaguar 2k6. Timing needs to
be updated if more mature info
is available.
Ping the Pacific through I²C
Reset the Pacific by pulling LOW the Pacific
hardware reset line during 100ms.
Release Pacific reset
and wait 200ms
No
Power-ok display high?
In case of an LCD set, check the
Power-OK display line
No
Yes
Log power-ok error and enter
protection
MP
Содержание 32PFL7403D/10
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