Circuit Descriptions, Abbreviation List, and IC Data Sheets
9.
9.5.11 Diagram B09B, STE100P (IC 7NA1)
Figure 9-17 Internal block diagram and pin configuration
Block Dia
g
ram
Pin Confi
g
uration
H_17650_0
8
1.ep
s
15010
8
NRZ To M
a
nche
s
ter
Encoder
MII
In
te
rf
a
ce
/
Co
n
tr
o
lle
r
10 TX
Filter
TRAN
S
MITTER
10/100
S
cr
a
m
b
ler
A
u
to
Negoti
a
tion
4B/5B
NRZ To NRZI
Encoder
Link P
u
l
s
e
Gener
a
tor
Bin
a
ry To MLT
3
Encoder
RECEIVER
10/100
P
a
r
a
llel to
S
eri
a
l
De
s
cr
a
m
b
ler
Code Align
4B/5B
NRZI To NRZ
Decoder
S
eri
a
l to
P
a
r
a
llel
NRZ To M
a
nche
s
ter
Encoder
Link P
u
l
s
e
Detector
S
MART
Squ
elch
10 TX Filter
Clock Recovery
Clock
Gener
a
tion
S
y
s
tem
Clock
Ad
a
ptive
E
qua
liz
a
tion
B
as
eLine
W
a
nder
Bin
a
ry To MLT
3
Decoder
Clock Recovery
REGI
S
TER
S
HW Config
Power Down
LED
S
RX Ch
a
nnel
TX Ch
a
nnel
TXP
TXN
RXP
RXN
MDC
MDIO
RXD[
3
:0]
RX_ER
RX_DV
RX_CLK
TX_CLK
TXD[
3
:0]
TX_ER
TX_EN
LED
S
HW
config
u
r
a
tion
pin
s
S
er
i
a
l M
a
n
a
ge
m
e
n
t
10M
b
/
s
100M
b
/
s
100M
b
/
s
10M
b
/
s
Loop
ba
ck
1
2
3
5
6
4
7
8
9
10
27
11
2
8
29
3
0
3
1
3
2
59 5
8
57 56
54
55
5
3
52 51 50 49
4
3
42
41
3
9
38
40
4
8
47
46
44
45
fde
mf0
mf1
mf
3
mf4
mf2
x2
gnd
a
vcc
a
gnd
a
nc
vcc
a
txn
gnd
a
gnde
pwrdwn
te
s
t
re
s
et
rip
nc
nc
nc
col
txd
3
txd2
txd1
tx_en
txd0
tx_clk
tx_er/txd4
rx_er/rxd4
gnde/i
rx_clk
rdx
3
mdc
mdio
vcce/i
ledr10
gnde/i
rx_dv
rxd0
rxd1
rdx2
vcce/i
22 2
3
24 25 26
60
cr
s
61
mdint
62
vcce/i
6
3
cfg1
64
cfg0
vcc
a
rxn
rxp
gnd
a
txp
17 1
8
19 20 21
3
7
3
6
3
4
33
3
5
ledtr
ledl
led
s
te
s
t_
s
e
ledc
12
1
3
14
15
16
vcc
a
iref
gnd
a
x1
vcc
a
S
TE100P
Содержание 32PFL7403D/10
Страница 59: ...Circuit Diagrams and PWB Layouts 59 Q528 2E LB 7 Layout LCD Supply 37 B 42 Top Side H_16750_070 eps 110108 ...
Страница 60: ...60 Q528 2E LB 7 Circuit Diagrams and PWB Layouts Layout LCD Supply 42 Bottom Side H_16750_071 eps 110108 ...
Страница 126: ...126 Q528 2E LB 7 Circuit Diagrams and PWB Layouts Personal Notes E_06532_013 eps 131004 ...