Pacific Power Source UPC-3, Руководство по эксплуатации

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SECTION 5 REMOTE OPERATION
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5.5.3 EVENT and STATUS REPORTING
Events and device Status may be queried by the Bus Controller through the following registers and
queues. Query commands are explicitly shown in this section for clarity.
NOTE: It is recommended that reading EVENT and STATUS registers and queues occur in the
following order. Reading any register or queue is optional. Indents indicate a hierarchy.
1. STB register, read via Serial Poll or
*STB? .
2. ESR register, read via *ESR? .
3. SYSTem:ERRor? queue.
4. STATus:OPERation:EVENt? register.
5. STATus:QUEStionable:EVENt? register.
NOTE: For most applications, the STB register and SYSTem:ERRor queue will satisfy status and error
reporting.
5.5.3.1 IEEE-488.2 STATUS REPORTING
Both IEEE-488 and serial port communications with UPC support the status reporting standards. Query
commands are explicitly shown for clarity. Refer to the ANSI/IEEE-488.2 1987 standard for more
information.
NOTE: <NRf> indicates Numeric Response format. See para. 5.2 Conventions regarding <NRf>.
STATUS BYTE REGISTER (STB)
STATUS conditions reported by the STATUS BYTE may be queried via the IEEE-488 Bus Serial Poll
function, or read directly using *STB?. The SRQ function will be invoked to signal the Bus controller that
service is requested, when an unmasked STATUS BYTE bit goes true. Note that no SRQ is generated
while in LOCAL CONTROL. *CLS clears the ESR and the STB. Refer to fig. 5.1.
The IEEE-488.2 Common Commands for
Status Reporting from the UPC are:
BIT NAME DEFINITION
7 SOS :STATus:OPERation register bit summary
6 MSS/RQS - MASTER SUMMARY
summarizes all STATUS BYTE bits (except bit 6) for *STB?, or,
- REQUEST SERVICE
indicates this device requested service when a Serial Poll was performed.
5 ESB STANDARD EVENT STATUS REGISTER bit summary
4 MAV MESSAGE AVAILABLE indicates Query response data is available
3 SQS :STATus:QUEStionable register bit summary
2 EEQ ERROR/EVENT QUEUE indicates an SCPI Error/Event message is
available
1 ----- NOT DEFINED
0 SHUTDOWN indicates Power Source SHUTDOWN
Setting a SERVICE REQUEST ENABLE (SRE) bit true unmasks the STATUS bit in the STB. Bit 6 of the
SRE is not applicable as the MASTER SUMMARY bit of the STB cannot be masked. The STB, SRE,
ESR and ESE registers are 8 bits each.