Oracle Acme Packet 4500, Руководство по установке и обслуживанию оборудования

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24 Acme Packet 4500 Hardware Installation and Maintenance Guide
COMPONENT OVERVIEW
Acme Packet4000 Series Hardware Architecture
The hardware architecture of the Acme Packet4000 series hardware architecture is
depicted below. The Acme Packet4000 series hardware is purpose built for SBC
applications and relies on state-of-the-art network processing and traffic
management components to deliver the necessary platform for delivering security
and scalable media processing.
The Network Processing (nP) subsystem is comprised of the network processors,
traffic management, and content addressable memory (CAM). This subsystem hosts
the media control module and is completely hardware based. Adjunct to the network
processing components are the QoS engine for monitoring bearer QoS metrics.
The signaling processor subsystem is comprised of the host subsystem and
associated memory (noted in red in the diagram). The session control functions
including the session signaling layer, call routing and management elements are
hosted on the signaling processor subsystem.
The separation of signaling and media processing is absolutely necessary for the
following reasons:
• Guarantee media processing will never overwhelm signaling processing.
Signaling processing performance is not impacted by media processing load as
it is with single more monolithic solutions based on general purpose computing
platforms.
• Protection of the signaling processing subsystem for overload and DoS attacks.
When DoS attacks are detected, these attacks are policed and isolated in
hardware.
The following architectural diagram is a logical representation of the Acme
Packet 4500. The Acme Packet 4500’s Network Processor is physically one
device.
Figure 2 - 28. Acme Packet 4500 Hardware Architecture