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©

 Semiconductor Components Industries, LLC,  2014

October, 2014 − Rev. 2

1

Publication Order Number:

EVBUM2277/D

EVBUM2277/D

KAI-2093 Image Sensor

Evaluation Timing

Specification

12-bit 20 MHz AFE

Altera Code Version Description

The Altera code described in this document is intended for

use in the KSC−1000 Timing Boar. The code is developed
specifically for use with the following system configuration:

Table 1. SYSTEM CONFIGURATION

Evaluation Board Kit

PN 4H0706

Timing Generator Board

PN 3F5051 (AD9845A 20 MHz)

KAI−2001/KAI−2020/KAI−2093 CCD Imager Board

PN 3F5121

Framegrabber Board

National Instruments Model PCI−1424

The 3F5051 Timing Generator Board features the

KSC−1000 Timing Generator chip. The KSC−1000
provides all of the signals necessary for an imaging system
using Full Frame (KAF) or Interline (KAI) family of image

sensors. It also provides the signals necessary for operation
of two analog front-end (AFE) chips, enabling independent
optimization of the AFE chips for dual channel readout
devices.

ALTERA CODE FEATURES/FUNCTIONS

The Altera Programmable Logic Device (PLD) serves as

a state machine, which performs a variety of functions.
Three basic functions are required, common to all CCD
image sensor configurations: serial input steering, AFE
default programming, and KSC−1000 default
programming. In addition, certain other functions specific to
the KAI−2093 Image Sensor are implemented.

Serial Input Steering

The 3-wire serial interface enters the Timing Board

through the DIO Interface connector, and is routed to the

PLD. The Altera PLD decodes the addressing of the serial
input, and steers the datastream to the correct device.
The serial input must be formatted so that the Altera PLD
can correctly decode and steer the data to the correct device.

The serial interface can be used to dynamically change the

operating conditions of the AFE or KSC−1000 chips by
reprogramming the appropriate registers. Reprogramming
these registers through the serial interface will have no effect
on the default settings that are automatically programmed
into these devices on power-up or board reset.

Table 2. SERIAL INPUT DEVICE SELECT

Device Select DS[2..0]

Serial Device

000

PLD

001

AFE1

010

AFE2

011

KSC−1000

100

(Not Used)

101

(Not Used)

110

(Not Used)

111

(Not Used)

EVAL BOARD USER’S MANUAL

www.onsemi.com

Содержание KAI-2093

Страница 1: ...ogrammable Logic Device PLD serves as a state machine which performs a variety of functions Three basic functions are required common to all CCD image sensor configurations serial input steering AFE d...

Страница 2: ...s when power is removed Figure 2 AFE Initialization Timing R W A0 A1 A2 Test D0 D1 D3 D4 SLOAD_AFE_x SDATA SCLK D5 D6 D7 D8 D9 D10 D2 The data for each AFE register is formatted into two bytes of data...

Страница 3: ...ariable PLD State Machine The Altera PLD contains a State Machine that parallels the operation of the KSC 1000 The PLD controls the KSC 1000 through the VD_TG output and monitors several of the KSC 10...

Страница 4: ...d remote digital inputs DIO 15 0 and a 3 wire serial interface through Timing Board connector J7 Timing Board signals and various outputs from the KSC 1000 Timing Generator The KSC 1000 outputs are mo...

Страница 5: ...d for KAI 2093 Operation VD_TG Control Signal to KSC 1000 ARSTZ Asynchronous Reset to KSC 1000 from DIO14 KAI 2093 TIMING CONDITIONS System Timing Conditions Table 6 SYSTEM TIMING Description Symbol T...

Страница 6: ...uts DIO 11 7 See Table 14 and Table 25 When changing the integration time the user must initiate a Board Reset for the change to take effect either by pressing the BOARD_RESET button S1 on the Timing...

Страница 7: ...Free Running Single Channel and Dual Channel modes and Frame Table 1 is used for Single Channel 2 2 Binning mode The default setting depends on the position of SW2 Table 10 REGISTER 0 DEFAULT SETTING...

Страница 8: ...t is used to halt execution of the KSC 1000 timing sequences and to enable programming of the registers The KSC 1000 Initialization sequence begins with setting the Memory Table Mode bit in Register 2...

Страница 9: ...DEFAULT SETTING DIO 11 7 Frame Flush Integration Free Running Mode Integrate Start Pulse Line Number 0 12 0 1 2040 Default No Pulse 1 1 8 966 2 1 4 828 3 3 8 690 4 1 2 552 5 5 8 414 6 3 4 276 7 7 8 13...

Страница 10: ...RG_OFFSET 0 5 0 0 RESET SH2_OFFSET 0 5 31 31 SHP1 SH1_OFFSET 0 5 31 31 SHP2 SH4_OFFSET 0 5 63 63 SHD1 SH3_OFFSET 0 5 63 63 SHD2 DATACLK1_OFFSET 0 5 42 42 ADCLK to AFEs DATACLK2_OFFSET 0 5 0 0 DATACLK...

Страница 11: ...Force INTG_STRT 0 0 0 0 3 4 Horizontal Binning Factor 0 0 0 0 5 HCLK_V Enable 0 0 0 0 6 LINE_VALID Enable 1 0 0 0 7 FRAME_VALID Enable 1 0 0 0 8 Video Amplifier Enable 0 0 0 0 9 AFE Clock Enable 1 1...

Страница 12: ...ee Figure 4 Table 20 LINE TABLE 0 DEFAULT SETTING CCD Signal Line Table Data Name LT0 Entry 0 1 2 3 4 5 6 Count 0 12 1 3 30 2 30 1 0 HCLK_H Enable 0 0 0 0 0 1 0 FDG V6 0 0 0 0 0 0 0 V5 0 0 0 0 0 0 0 V...

Страница 13: ...rval followed by Horizontal Register readout See Figure 7 Table 23 LINE TABLE 3 DEFAULT SETTING CCD Signal Line Table Data Name LT3 Entry 0 1 2 3 4 5 6 7 8 9 Count 0 12 1 1 30 1 30 1 30 1 30 0 HCLK_H...

Страница 14: ...out through the output amplifier s Figure 4 Line Table 0 Default Timing LT0 Entry V1_CCD V2_CCD 0 1 2 3 5 1 3 30 2 1 30 Pix Counts not to scale HCLK_ENABLE VLOW VMID VLOW VMID H1A_CCD H2A_CCD 4 TVD T...

Страница 15: ...asserted twice per line This effectively sums two pixels worth of charge into each Horizontal CCD pixel After the binning line transfer the Horizontal clocks are run in Binning Mode Figure 7 Line Tabl...

Страница 16: ...epeats with the next Line Transfer sequence Execute LT1 DIODE XFR Count 1 DIO 11 7 1 2 7 Set INTEGRATE Wait for INT ctr Execute LT0 LINE XFR Count 1214 Wait for FRAME_VALID falling edge Execute LT5 Wa...

Страница 17: ...RANSFER PLD STATE TIMED_INTEGRATION Electronic Shutter Timing The electronic shutter timing is controlled by the values in Register 3 of the KSC 1000 There are two methods of actuating the Electronic...

Страница 18: ...reset to VRD the Reset Drain voltage See the KAI 2093 Device Specification References for further details In order to correctly convert the output amplifier voltage to digital data the AFE clocks must...

Страница 19: ...Pulse Line Number value of the KSC 1000 Register 4 The Altera PLD has 8 pre programmed Shutter settings controlled through the DIO 11 7 bits as shown in Table 14 and Table 25 These settings result in...

Страница 20: ...2040 No Shutter 0 140 13 50 2040 No Shutter 0 165 14 70 2040 No Shutter 0 185 15 100 2040 No Shutter 0 215 16 200 2040 No Shutter 0 315 17 300 2040 No Shutter 0 415 18 400 2040 No Shutter 0 515 19 500...

Страница 21: ...igure 16 Free Running Mode Default Integration Timing V1_CCD V2_CCD VD_TG FRAME_VALID LINE_VALID FT0 Entry 2 0 1 0 Line Table 1 1104 Counts 1 4 x not to scale INTEGRATE 0 DIO 11 7 1ms Clock Integratio...

Страница 22: ...nts 1 4 x not to scale INTEGRATE DIO 11 7 1ms Clock Integration Count 0 VES shutter 1 Shutter Line 966 1 2 3 4 5 965 966 1104 1103 Figure 18 Free Running Mode Extended Integration Timing V1_CCD V2_CCD...

Страница 23: ..._OUT2 9 10 9 10 IMAGER_IN10 FDG V1 TIMING_OUT3 13 14 13 14 IMAGER_IN9 V3RD V2 TIMING_OUT4 17 18 17 18 IMAGER_IN8 V3 TIMING_OUT5 21 22 21 22 IMAGER_IN7 V2 V4 TIMING_OUT6 25 26 25 26 IMAGER_IN6 V1 RG TI...

Страница 24: ...Digital Out Analog Front End Op Amp Buffer Av 1 25 5V 5V 5V 5V CCD AFE 2 stage prog gain Timing Board Imager Board WARNINGS AND ADVISORIES When programming the Timing Board the Imager Board must be di...

Страница 25: ...under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applicat...

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