background image

AN-6094 
 

© 2012 Fairchild Semiconductor Corporation 

 

www.fairchildsemi.com 

Rev. 1.0.0  •  9/27/12 

16 

5. PCB Layout Guidelines

Printed Circuit Board (PCB) layout and design are very 
important for switching power supplies where the voltage 
and current change with high dv/dt and di/dt. Good PCB 
layout minimizes excessive EMI and prevents the power 
supply from being disrupted during surge / ESD tests. The 
following guidelines are recommended for layout designs. 

 

To improve EMI performance and reduce line 
frequency ripple, the output of the bridge rectifier 
should be connected to capacitors C

DL2

 and C

DL1

 first, 

then to the transformer and MOSFET. 

 

The primary-side high-frequency current loop is 

C

DL2

 

– Transformer – MOSFET – R

CS

 – C

DL2

. The area 

enclosed by this current loop should be as small as 
possible. The trace for the control signal (FB, CS, and 
GATE) should not go across this primary high-
frequency current loop to avoid interference. 

 

Place R

HV

 for protection from the inrush spike on the 

HV pin (100 k

 is recommended).  

 

R

CS

 should be connected to the ground of C

DL2 

directly. Keep the trace short and wide (Trace 

4

1

and place it close to the CS pin to reduce switching 
noise. High-voltage traces related to the drain of the 
MOSFET and the RCD snubber should be away from 
control circuits to prevent unnecessary interference. If 
a heat sink is used for the MOSFET, connect this heat 
sink to ground. 

 

As indicated by 

2

, the area enclosed by the 

transformer auxiliary winding, D

DD

 and C

DD

, should 

be small. 

 

Place 

C

DD

C

S

R

S2

C

FB, 

and 

R

BF

 close to the controller 

for good decoupling and low switching noise. 

 

As indicated by 

3

, the ground of the control circuits 

should be connected at a single point first, then to 
other circuitry.  

 

Connect ground in 

3

2

4

sequence. This helps 

avoid common impedance interference for the sense 
signal.  

 

Regarding the ESD discharge path, use the shortcut 
pad between the AC line and the DC output 
(recommended). Another method is to discharge the 
ESD energy to the AC line through the primary-side 
main ground 

1

. Because ESD energy is delivered from 

the secondary side to the primary side through the 
transformer stray capacitor or the Y capacitor, the 
controller circuit should not be placed on the discharge 
path. 

5

 shows where the point-discharge route can be 

placed to effectively bypass the static electricity energy.  

 

For the surge path, select a fusible resistor of wire-
wound type to reduce inrush current and surge energy. 
Use 

π

 input filter (two bulk capacitor and one 

inductance) to share the surge energy.  

 

 

Figure 24. Recommended Layout  

 

Содержание Fairchild FAN302HL

Страница 1: ...y ON Semiconductor Typical parameters which may be provided in ON Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time Al...

Страница 2: ...nsformer and controlled with an internal compensation circuit This removes the output current sensing loss and eliminates all external current control circuitry facilitating a higher efficiency power...

Страница 3: ...ycle As seen in Figure 2 the outputs of two comparators PWM I and PWM V are combined with the OR gate and used as a reset signal of flip flop to determine the MOSFET turn off instant The lower signal...

Страница 4: ...on range since the output current can be properly estimated only in DCM as described in Section 2 As seen in Figure 5 the MOSFET conduction time tON decreases as output voltage decreases in CC Mode wh...

Страница 5: ...FF C The overall power conversion efficiency should be estimated to calculate the input power and maximum DC link voltage ripple If no reference data is available use the typical efficiencies in Table...

Страница 6: ...nt B are given as N O B O IN B FF B V I P E 9 N O B O IN T B FF S B V I P E 10 The overall efficiency at operating point C can be approximated as N O C O F FF C FF N O C F O V V V E E V V V 11 where V...

Страница 7: ...he MOSFET drain to source voltage waveforms When the MOSFET is turned off the sum of the input DC link voltage VDL and the output voltage reflected to the primary side is imposed across the MOSFET cal...

Страница 8: ...the power consumption of the IC by minimizing VDD at no load condition NA NS is determined as 1 6 STEP 4 Design the Transformer Figure 12 shows the MOSFET conduction time tON diode current discharge...

Страница 9: ...point C is given as min 1 1 DL C S OFF C ON C S C P O C F V N t t f N V V 28 The non conduction time should be larger than 15 of switching period considering the transformer variation and frequency ho...

Страница 10: ...as 2 P CCR CS N S O N V R N I K 31 where VCCR is 2 43 V and K 12 and 10 5 V for UL and HL respectively The voltage divider RVS1 and RVS2 should be determined so that VS is about 2 5 V at 85 of diode c...

Страница 11: ...s related to the power dissipation in the clamping circuit Setting the voltage overshoot too low can lead to severe power dissipation in the clamping circuit For reasonable clamping circuit design vol...

Страница 12: ...network is less than the designed value due to this effect 2 m OSS L C 2 LK OSS L C Figure 18 Drain Voltage Waveform Design Example Assuming that 700 V MOSFET is used the voltage overshoot to limit th...

Страница 13: ...g frequency Design Example Assuming a 330 F tantalum capacitor with 100 m ESR for the output capacitor the voltage ripple on the output is 5 59 PK P C DS S N I I A N 2 0 592 2 N DIS A C O O C C O C t...

Страница 14: ...L 51 Note that the effect of slope compensation is weaker at high line which increases the gain of control to output transfer function Thus the high line is the worst case for feedback loop design Si...

Страница 15: ...or is used STEP 11 Choose Startup Resistor for HV Pin Figure 22 shows the high voltage HV startup circuit for FAN302 applications Internally the JFET is used to implement the high voltage current sour...

Страница 16: ...ror amplifier output in normal operation During the load transient or abnormal condition such as output short the error amplifier can be saturated HIGH and the drain current is regulated by the pulse...

Страница 17: ...ge traces related to the drain of the MOSFET and the RCD snubber should be away from control circuits to prevent unnecessary interference If a heat sink is used for the MOSFET connect this heat sink t...

Страница 18: ...elds 18 H of effective leakage inductance Clamping circuit resistor R10 is adjusted to 390 k based on test results from the actual power supply Note that the sensing resistor is fine tuned to 1 2 base...

Страница 19: ...Start Pin End Pin Turns W1 1 2 2UEW 0 15 2 8 2 W2 4 5 2UEW 0 12 1 22 0 22 1 22 3 W3 Fly Fly TEX E 0 4 1 5 3 Pin Specifications Remark Primary Side Inductance 4 5 530 H 7 100 kHz 1 V Primary Side Effec...

Страница 20: ...2 shows the loss breakdown for the standby power consumption for 90 VAC and 264 VAC Figure 31 shows the measured output voltage and output current curve The output current is regulated between 1 A and...

Страница 21: ...R USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS NOR THE RIGHTS OF OTHERS LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE...

Страница 22: ...the rights of others ON Semiconductor products are not designed intended or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices wit...

Отзывы: