AN-6094
© 2012 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev. 1.0.0 • 9/27/12
14
(Design Example)
In STEP-8, the post LC filter is
designed with two 330 µF capacitors and a 1.8 µH
inductor. Since the resonance frequency of the post LC
filter is 9.2 kHz, the bandwidth of the feedback loop
should be less than 1/3 of the cut-off frequency to
minimize the phase drop caused by the post LC filter.
Thus, the target bandwidth of the feedback loop is
determined as around 3 kHz.
To simplify analysis, the inductor of the post filter is
ignored, since the bandwidth is below the cutoff
frequency of post LC filter. The effective output
capacitance and its effective series resistance are given as:
330
2 660
OUT
C
F
F
μ
μ
=
× =
100
/ 2 50
ES
R
m
m
=
Ω =
Ω
The slope of current sensing signal for high line is
obtained as:
373 1.2
0.845 /
530
DL
CS
m
V
R
V
m
V
s
L
H
μ
μ
⋅
⋅
=
=
=
The slope of internal slope compensation is obtained as:
max
0.3
0.3
0.066 /
1/
7.14
0.64
a
S
V
V
m
V
s
f
D
s
μ
μ
=
=
=
×
×
Then, the gain G
V
for high line and maximum load
condition is obtained as:
1
3
3
N
O
V
PK
a
CS DS
V
m
G
m m
R I
= ⋅
⋅
=
+
The system pole and zero are obtained as:
2
727
/
p
L
OUT
rad s
R C
ω
=
=
1
30,300
/
Z
ES
OUT
rad s
R C
ω
=
=
With R
F
=0
Ω
, C
FR
=10 nF, R
bias
=1 k
Ω
, R
F1
=50 k
Ω
,
C
FB
=4nF (including output capacitance of opto-
transistor), and R
FB
=42 k
Ω
; 3 kHz bandwidth with 53
°
phase margin is obtained. For C
FB
, output capacitance of
an opto-transistor is assumed to be 3 nF and a 1 nF
external capacitor is used.
[STEP-11] Choose Startup Resistor for HV Pin
Figure 22 shows the high-voltage (HV) startup circuit for
FAN302 applications. Internally, the JFET is used to
implement the high-voltage current source, whose
characteristics are shown in Figure 23. Technically, the
HV pin can be directly connected to the DC link (V
DL
).
However, to improve reliability and surge immunity, it is
typical to use a ~100 k
Ω
resistor between the HV pin and
the DC link. The actual HV current with a given DC link
voltage and startup resistor is determined by the
intersection point of V-I characteristics line and load line,
as shown in Figure 23.
During startup, the internal startup circuit is enabled and
the DC link supplies the current, I
HV
, to charge the hold-
up capacitor, C
DD
, through R
HV
. When the V
DD
voltage
reaches V
DD-ON
, the internal HV startup circuit is disabled
and the IC starts PWM switching. Once the HV startup
circuit is disabled, the energy stored in C
DD
should supply
the IC operating current until the transformer auxiliary
winding voltage reaches the nominal value. Therefore,
C
DD
should be properly designed to prevent V
DD
from
dropping to V
DD-OFF
before the auxiliary winding builds up
enough voltage to supply V
DD
.
The startup time with a given C
DD
capacitor is given as:
.
(
)
DD
DD ON
start
HV
DD ST
C V
t
I
I
−
=
−
(53)
Figure 22. HV Startup Circuit
500V
100V
200V
300V
400V
3.5mA
I
HV
0.8mA
1.5mA
DL
HV
HV
HV
V
V
I
R
−
=
DL
HV
V
R
DL
V
V
HV
Figure 23. V-I Characteristics of HV Pin
(Design Example)
With 100 k
Ω
HV resistor and 33 µF
V
DD
capacitor, the maximum startup time is:
.
33 16
1.32s
(
)
0.8
0.4
DD
DD ON
start
HV
DD ST
C V
V
t
I
I
mA
mA
μ
−
⋅
=
=
=
−
−
