AN-6094
© 2012 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev. 1.0.0 • 9/27/12
6
[STEP-2] Determine the DC Link Capacitor
(C
DL
) and the DC Link Voltage Range
It is typical to select the DC link capacitor as 2-3 µF per
watt of input power for universal input range (90-
264 V
AC
) and 1 µF per watt of input power for European
input range (195~265 V
rms
). With the DC link capacitor
chosen, the minimum DC link voltage is obtained as:
@
min
min 2
@
(1
)
2 (
)
IN
A
ch
DL
A
LINE
DL
L
P
D
V
V
C
f
−
=
⋅
−
⋅
(15)
where V
LINE
min
is the minimum line voltage; C
DL
is the
DC link capacitor; f
L
is the line frequency; and D
ch
is
the DC link capacitor charging duty ratio defined as
shown in Figure 9, which is typically about 0.2.
The maximum DC link voltage is given as:
max
max
2
DL
LINE
V
V
=
⋅
(16)
where V
LINE
max
is the maximum line voltage.
The minimum DC link voltage and its ripple change with
input power. The minimum input DC link voltage at
operating point B is given as:
@
min
min 2
@
(1
)
2 (
)
IN
B
ch
DL
B
LINE
DL
L
P
D
V
V
C
f
−
=
⋅
−
⋅
(17)
The minimum input DC link voltage at operating point C
is given as:
@
min
min 2
@
(1
)
2 (
)
IN
C
ch
DL
C
LINE
DL
L
P
D
V
V
C
f
−
=
⋅
−
⋅
(18)
Figure 9. DC Link Voltage Waveforms
(Design Example)
By choosing two 6.8 µF capacitors
in parallel for the DC link capacitor, the minimum and
maximum DC link voltages for each condition are
obtained as:
@
min
min 2
@
2
6
(1
)
2 (
)
8.22(1 0.2)
2 (90)
90
2 6.8 10
60
IN
A
ch
DL
A
LINE
DL
L
P
D
V
V
C
f
V
−
−
=
⋅
−
⋅
−
=
⋅
−
=
⋅
×
⋅
max
2 264 373
DL
V
V
=
⋅
=
@
min
min 2
@
2
6
(1
)
2 (
)
7.07(1 0.2)
2 (90)
96
2 6.8 10
60
IN
B
ch
DL
B
LINE
DL
L
P
D
V
V
C
f
V
−
−
=
⋅
−
⋅
−
=
⋅
−
=
⋅
×
⋅
@
min
min 2
@
2
6
(1
)
2 (
)
2.46(1 0.2)
2 (90)
117
2 6.8 10
60
IN
C
ch
DL
C
LINE
DL
L
P
D
V
V
C
f
V
−
−
=
⋅
−
⋅
−
=
⋅
−
=
⋅
×
⋅
[STEP-3] Determine Transformer Turns
Ratio
Figure 10 shows the MOSFET drain-to-source voltage
waveforms. When the MOSFET is turned off, the sum of
the input DC link voltage (V
DL
) and the output voltage
reflected to the primary side is imposed across the
MOSFET, calculated as:
max
nom
DS
DL
RO
V
V
V
=
+
(19)
where V
RO
is reflected output voltage, defined as:
(
)
p
N
RO
O
F
s
N
V
V
V
N
=
+
(20)
where N
P
and N
S
are number of turns for the primary
side and secondary side, respectively.
When the MOSFET is turned on; the output voltage,
together with input voltage reflected to the secondary, are
imposed across the secondary-side rectifier diode
calculated as:
max
nom
N
S
D
DL
O
P
N
V
V
V
N
=
+
(21)
As observed in Equations (19), (20), and (21); increasing
the transformer turns ratio (N
P
/ N
S
) increases voltage
stress on the MOSFET while reducing voltage stress on
the rectifier diode. Therefore, the N
P
/ N
S
should be
determined by the trade-off between the MOSFET and
diode voltage stresses.
The transformer turns ratio between the auxiliary winding
and the secondary winding (N
A
/ N
S
) should be
determined by considering the allowable IC supply
voltage (V
DD
) range. The V
DD
voltage varies with load
condition, as shown in Figure 11, where the minimum
V
DD
typically occurs at minimum load condition. Due to
the voltage overshoot of the auxiliary winding voltage
caused by the transformer leakage inductance; the V
DD
at
operating point C tends to be higher than the V
DD
at
minimum load condition.
The V
DD
at minimum load condition is obtained as:
min
(
)
A
DD
O
F
FA
S
N
V
V
V
V
N
≅
+
−
(22)
where V
FA
is the diode forward-voltage drop of the
auxiliary winding diode.
The transformer turns ratio should be determined such
that V
DD
min
is higher than the V
DD
UVLO voltage, such as:
max
(
)
A
O
F
FA
UVLO
MRGN
S
N
V
V
V
V
V
N
+
−
>
+
(23)
Since the V
DD
min
is related to standby power consumption,
smaller N
A
/ N
S
leads to lower standby power
consumption. However, 2~3 V margin (V
MRGN
) should be
