AN-6094
© 2012 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev. 1.0.0 • 9/27/12
10
The recommendation for R
VS1
design is to set R
VS1
such
that the minimum on time curve of Figure 16 can be fully
utilized for the universal line range. It is typical to select
R
VS1
such that I
VS.ON
is around 180 µA for the minimum
line voltage.
Figure 16. Minimum On-Time vs. VS Pin Current (UL)
A bypass capacitor of 22~68 pF placed closely between
the VS and GND pins is recommended to bypass the
switching noise. Too large a capacitor distorts V
S
voltage
and deteriorates the output current regulation. The RC
time constant of the bypass capacitor and voltage divider
resistor should be <10% of switching period, given as:
1
2
1
(
//
)
10
RC
VS
VS
VS
S
R
R
C
f
τ
=
⋅
<
(34)
(Design Example)
The sensing resistor is obtained as:
66 2.43
1.1
2
2 5 1.2 12
P
CCR
CS
N
S O
N
V
R
N I
K
×
×
=
=
= Ω
×
× ×
×
Note that the sensing resistor is fine-tuned to 1.2
Ω
in the
final schematic based on the test results of actual
prototype power supply.
The voltage divider network is determined as:
1
.
2
8 5 0.1
(
1) (
1) 2.26
2.5
5
2.5
VS
O
F SH
A
VS
S
R
V
V
N
R
N
+
+
=
⋅
− = ⋅
− =
To set I
VS.ON
around 180 µA for the minimum DC link,
calculate the R
VS1
as:
.
1
2
1
1
0.7
(
0.7)
180
(
2 90 0.7) 0.7 2.26
98
180
A
VS ON
DL
P
VS
VS
A
P
VS
N
I
V
A
N
R
R
N
N
R
k
A
μ
μ
=
+
+
=
⋅ +
+
×
=
=
Ω
By setting R
VS1
=91 k
Ω
, R
VS2
is obtained as 40 k
Ω
.
The bypass capacitor should be:
1
2
1
26
10 (
//
)
VS
S
VS
VS
C
pF
f R
R
<
=
Thus, a 22 pF capacitor is selected for C
VS
.
[STEP-6] Design the RCD Clamping Circuit
in the Primary Side
When the MOSFET in the flyback converter is turned off, a
high-voltage spike is generated across the MOSFET due to
the transformer leakage inductance. This excessive voltage
can lead to an avalanche breakdown and, eventually, failure
of the MOSFET. Therefore, an RCD clamping circuit must
limit the voltage, as shown in Figure 17. The voltage
overshoot (V
OS
) is related to the power dissipation in the
clamping circuit. Setting the voltage overshoot too low can
lead to severe power dissipation in the clamping circuit. For
reasonable clamping circuit design, voltage overshoot (V
OS
)
is typically 1~2 times the reflected output voltage.
It is typical to have a margin of 10~20% of the breakdown
voltage for maximum MOSFET voltage stress. The
maximum voltage stress of the MOSFET is given as:
max
max
DS
DL
RO
OS
V
V
V
V
=
+
+
(35)
When the drain voltage of the MOSFET reaches the
voltage of node X (sum of DC link voltage and clamping
capacitor voltage), the clamping diode is turned on to
limit the drain voltage. It is assumed that the clamping
capacitor is large enough that its voltage does not change
significantly during one switching cycle.
For medium-power and high-power applications where
the leakage inductance energy is much larger than the
energy stored in the effective output capacitance of the
MOSFET, the output capacitance of the MOSFET is
generally ignored when designing the clamping circuit.
However, for low-power applications where the leakage
inductance energy is almost the same as, or smaller than,
the energy stored in the effective output capacitance of the
MOSFET, the output capacitance of the MOSFET should
be considered for clamping circuit design. Especially for
low-power applications of less than 10 W, the transformer
typically has a large number of turns, resulting in large
inter-winding capacitance. This significantly contributes
to the effective output capacitance of the MOSFETs,
affecting the operation of the clamping circuit.
Considering the loading effect of the output capacitance
of the MOSFET, the peak current of clamping circuit is
given as:
2
2
(
)
PK
PK
OSS
CL
DS
OS
LK
C
I
I
V
L
=
−
(36)
where V
OS
is the voltage overshoot of the drain voltage,
as illustrated in Figure 17.
The power dissipated in the RCD network is given as:
2
1
(
)
2
PK
RO
OS
CLMP
S
LK
CL
OS
V
V
P
f L
I
V
+
=
(37)
where I
CL
PK
is the peak clamping diode current at full
load; L
LK
is the leakage inductance.
