Inverter Interface
SECTION 5
5-4-8
Operations with Command Bit Combinations
The table below shows the behaviour of the system when a command bit of
one type (read or write) is set before clearing the previous command bit of
the other type.
Status
Transfer
Command
Bit 2
Transfer
Busy
Transfer
Completion
Transfer
Error
Transfer
Command
Bit 1
Busy error
occurs.
Transfer
operation is
aborted.
Busy error
occurs.
Transfer
operation is
aborted.
Busy error
occurs.
Command is
not executed.
Error is cleared
and command
is executed.
After the completion of a command the command bit must be cleared first be-
fore issuing the next command. Not clearing the command bit has the follow-
ing consequences:
•
Sending a write transfer command immediately after a read transfer com-
mand is processed.
•
Sending a read transfer command immediately after a write transfer com-
mand is not processed.
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