Maxiflex P3 PAC User Manual
30
-© Omniflex
UMM126XR18.pdf
6. The Data Interchange Table explained
6.1 DIT Table Overview
Data Interchange Tables (DIT’s) are the “crossroads” for data in the Maxiflex system. A DIT
is an array of 16 bit registers accessible from any function or communications port in the
system.
The P3 CPU has a DIT in which all the configuration settings and dynamic data, including I/O
can be accessed. Any exchange of data between functions in the CPU and with the outside
world takes place t
hrough the CPU’s DIT.
Intelligent I/O Modules such as NIM’s also each have a DIT. A portion of the intelligent I/O
modules’ DIT Registers are overlaid on to the CPU DIT, and appear as if they are part of the
CPU’s DIT. This extended DIT addressing is used to directly access data in any intelligent
modules installed on the Maxiflex base as if the data is in the CPU.
6.2 DIT Table Layout
The Data Interchange Table in the P3 CPU provides access to up to 65,500 16-bit data
registers used for reading and writing all configuration and dynamic data in the CPU and all
of its I/O modules.
Some of these register addresses expose registers in the Intelligent I/O modules of the
system as if they are part of the CPU’s DIT. This is known as “extended DIT access”. There
are two modes of operation of extended DIT access:
In Extended Address Mode 1, each of the 15 I/O Module Slots is allocated 2000 Registers in
the CPU address space.
In Extended Address Mode 2, only the first 7 I/O Module Slots are allocated 4000 Registers
each in the CPU address space.
The following tables show the address map of the DIT table for an entire MAXIFLEX system
as viewed from the P3 CPU in each Extended Addressing mode.
This table shows the CPU DIT mapping of the first 2000 registers of any NIM modules
installed on the Maxiflex base:
Maxiflex Local Master Rack
Maxiflex
Slot:
CPU
Dynamic
Data
Space
CPU
Config
Data
Space
I/O
Slot
1
I/O
Slot
2
I/O
Slot
3
I/O
Slot
4
I/O
Slot
5
I/O
Slot
6
I/O
Slot
7
DIT Start
Address:
0
60,000
30,000
32,000 34,000
36,000 38,000
40,000 42,000
DIT End
Address:
29,999
65499
31,999
33,999 35,999
37,999 39,999
41,999 43,999
No. of
Registers
30,000
5,499
2,000
2,000
2,000
2,000
2,000
2,000
2,000
Table 6.1: DIT Address Map of the P3 CPU and Master Rack in Extended DIT Address Mode 1