Page: 19
Service Guide OL830
Chapter 2 Principles of Operation
2.2.03 Main Controller Board (APSM)
The Main Controller Board (APSM) consists of the CPU, RAM, ROM, Serial Communications
Controller (SCC), FIFO, EEPROM and Gate Array.
The CPU is a MC68000 with a clock frequency of 12.5MHz.
Sixteen 1 Mbit (1 bit x 1 Mbit) dynamic RAM chips are mounted as resident RAM (total 2Mbytes).
Two 4 Mbit EPROMs store program data for PostScript operation. Two 4 Mbit EPROMs are
located on the optional emulation PCB.
The IOA (Input/Output Adapter) IC12 (MSM75V036) controls the Operation Panel interface,
Printer Unit interface, read/write operations of FIFO (IC13) and the EEPROM IC1 (X2404).
The FIFO (First in-First out Buffer) connects the CPU to the video interface. The FIFO has a
capacity of over 2 lines (2 rasters). The data written to the FIFO by the CPU is sequentially read
according to the VIDEO I/F synchronous signal.
The Serial Communications Controller - SCC - (Z8530H8) controls the RS-232C interface,
RS-422 interface, and the AppleTalk interface. The RS-422 and AppleTalk interfaces use the
same connector. Although the RS-422 and AppleTalk interfaces are physically the same, they use
different protocols and are usable only in the PostScript mode.
Copyright 1997, Okidata, Division of OKI America, Inc. All rights reserved. See the OKIDATA Business
Partner Exchange (BPX) for any updates to this material. (http://bpx.okidata.com)
