12-3
PC-500 user’s manual
LED signaling and “beep” codes
Table 12-2
Phoenix BIOS beep codes (cont’d)
Diagnostic
port output
Beep
codes Description of test or failure
28h
N/A
CMOS power-fail and checksum checks in-progress
29h
N/A
CMOS config info. validation in-progress
2Bh
3-3-4
Screen memory test in-progress or failure
2Ch
3-4-1
Screen initialization in-progress or failure
2Dh
3-4-2
Screen retrace tests in-progress or failure
2Eh
N/A
Search for video ROM in-progress
30h
N/A
Screen believed operable:
30h
N/A
Screen believed running w/video ROM
31h
N/A
Monochromatic screen believed operable
32h
N/A
40-column color screen believed operable
33h
N/A
80-column color screen believed operable
34h
4-2-1
Timer tick interrupt test in-progress or failure
35h
4-2-2
Shutdown test in-progress or failure
36h
4-2-3
Gate A20 failure
37h
4-2-4
Unexpected interrupt in protected mode
38h
4-3-1
RAM test in-progress or failure above address 0FFFFh
3Ah
4-3-3
Interval timer channel 2 test in-progress or failure
3Bh
4-3-4
Time-of-day clock test in-progress or failure
3Ch
4-4-1
Serial port test in-progress or failure
3Dh
4-4-2
Parallel port test in-progress or failure
3Eh
4-4-3
Math coprocessor test in-progress or failure
50h
N/A
Beginning of CSET_INIT
51h
N/A
Loading the RCM table
52h
N/A
Loading the FCM table, doing DMC
53h
N/A
Entering CSET_BFR_VIDROM (before video ROM)
54h
N/A
Entering CSET_BFR_SIZMEM (before memory sizing)
55h
N/A
Entering CSET_AFT_MTEST (before memory test)
56h
N/A
Entering CSET_AFT_CMCFG (before CMOS
configuration check)
57h
N/A
Entering CSET_BFR_OPROM (before option ROM
scan)
Содержание PC-500
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