NXP Semiconductors QorIQ LS1028A, Справочное руководство, Страница: 60 / 112

Table 35. Qixis Register Memory Map (continued)
Offset Register
Width
(In bits)
Access Reset value
090h
Interrupt Status 0 (IRQSTAT0) 8 RO 11xx1111b
091h
Interrupt Status 1 (IRQSTAT1) 8 RO xxxxx1xxb
092h
Interrupt Status 2 (IRQSTAT2) 8 RO xxxxxxxb
09Dh
Interrupt Drive 5 (IRQDRV5) 8 RW 00000000b
0D8h
Core Management Address (CMSA) 8 RW 00000000b
0D9h
Core Management Data (CMSD) 8 RW 00000000b
4.1 Register Conventions
An undefined register address does not have any defined register value. Reads and writes to such addresses should be avoided.
If you attempt to read such addresses, undefined data is returned. Undefined register addresses may be defined in the future.
For registers which do not define all bits, reserved bits behave as follows:
Reserved Bits
Register Recommended Actions
DUTCFG Read as 1. Write ones to unused bits.
others Read as 0. Write zeroes to unused bits.
Future definitions of reserved bits will maintain backward compatibility with the above rules.
4.2 Resets
The reset values for registers are defined as follows:
Reset Actions
Term Reset Action
NONE Register cannot be reset. Applies to read-only registers.
ARST Auxiliary Reset: registers are reset when the system powers up with standby power, and is never altered
by hardware again. Software writes are preserved.
CRST Control Reset: registers are not reset except under exceptional situations, such as power cycles or
watchdog timeout.
Table continues on the next page...
Qixis Programming Model
QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018
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