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4.26 Clock Control Registers
The clock control registers control programmable clock synthesizers used to supply clocks to the processor and associated
peripherals.
4.27 Clock Speed 1 (CLK_SPD1)
Address
Register
Offset
CLK_SPD1
030h
Function
The CLK_SPD1 register is used to report the user-selectable speed settings (typically from switches) for the SYSCLK and
DDRCLK clocks.
Values in the CLK_SPD1 register are used by boot software accurately initialize timing-dependent parameters, such as for UART
baud rates, I2C clock rates, and DDR memory timing.
Diagram
Bits
7
6
5
4
3
2
1
0
R
SYSCLK
W
NONE
0000
0010
Fields
Field
Function
7-4
-
Reserved.
3-0
SYSCLK
SYSCLK Rate Selection:
0010= 100.00 MHz (fixed)
Other values are Reserved.
Qixis Programming Model
QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018
80
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NXP Semiconductors
Содержание QorIQ LS1028A
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