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P5040/P5020 Reference Design Board User Guide, Rev. 0
8 Freescale Semiconductor
Architecture
5.1.1 DDR
The P5040/P5020RDB contains a number of DDR-related features, as follows:
• Memory controller capable of supporting DDR3 and DDR3-LV devices
• Supports DDR3 using one 8GB, 1.35V/1.5V 204-pin Micron MT18KSF1G72HZ-1G6E2
SODIMM module @ 1333/1600 Mbps data rate at 72-bit, and ECC support
• Memory interface includes all necessary termination and IO power and is routed in order to achieve
maximum performance on the memory bus.
• As noted in the table below, P5040/P5020 has a dual DDR controller connected to dual DDR3
SODIMM slots.
Ethernet Section 5.1.3, “Ethernet Controller (EC) Interfaces ”
IEEE 1588 Section 5.1.4, “Support for IEEE Std 1588
™
Protocol ”
Serial interfaces Section 5.1.5, “Serial Interfaces ”
eSDHC Section 5.1.7, “enhanced Secure Digital Host Controller
(eSDHC) & embedded Multi Media Controller (eMMC)
”
SPI Section 5.1.6, “enhanced Serial Peripheral Interface (eSPI) ”
UART Serial Ports Section 5.1.8, “UART Serial Ports ”
USB Section 5.1.9, “USB Interfaces ”
DMA Section 5.1.10, “DMA Controllers ”
eOpenPIC Section 5.1.11, “eOpenPIC Interrupt Controller ”
GPIO Section 5.1.12, “GPIO Signals ”
System Control Section 5.1.13, “Control Group ”
I2C Section 5.1.14, “I
2
C ”
EM1 and EM2 Management Section 5.1.15, “EM1 and EM2 Management Buses ”
Debug/Power Management Section 5.1.17, “Debug Features ”
Clock Section 5.1.18, “Clock ”
Thermal Section 5.1.19, “Temperature Anode and Cathode ”
Power Section 5.1.20, “Power ”
Table 4. DDR Features
DDR Feature Description
DDR3 Topology Each controller connects to its own SODIMM slot.
Supports write-leveling intended to help determine timing skews.
Termination All input signal lines are terminated at the DIMM modules.
Additional termination is not required.
Table 3. P5040/P5020 Pin Groupings Summary (continued)
Signal Group Details